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PDF HYB39S256800T Data sheet ( Hoja de datos )
| Número de pieza | HYB39S256800T | |
| Descripción | (HYB39S256xxx) 256 MBit Synchronous DRAM | |
| Fabricantes | Siemens Semiconductor | |
| Logotipo |  |
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256 MBit Synchronous DRAM
HYB 39S256400/800/160T
Preliminary Information
• High Performance:
-8 -8B -10 Units
fCK 125 100 100 MHz
tCK3 8 10 10 ns
tAC3
6
6
7 ns
tCK2 10 12 15 ns
tAC2
6
7
8 ns
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3, 4
•www.DataSheet4U.com Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length:
1, 2, 4, 8
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write control (× 4, × 8)
• Data Mask for byte control (× 16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 8192 refresh cycles/64 ms 7,8 µ
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface versions
• Plastic Packages:
P-TSOPII-54 400mil width (× 4, × 8, × 16)
• -8 part for PC100 2-2-2 operation
-8B part for PC100 3-2-3 operation
-10 part for PC66 2-2-2 operation
The HYB 39S256400/800/160T are four bank Synchronous DRAM’s organized as
4 banks × 16 MBit × 4, 4 banks × 8 MBit × 8 and 4 banks × 4 MBit × 16 respectively. These syn-
chronous devices achieve high speed data transfer rates for CAS latencies by employing a chip
architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is fabricated with SIEMENS’ advanced 256 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V ± 0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
1
1998-10-01
1 page  
HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Column
Address Counter
Column Addresses
A0 - A9, AP,
BA0, BA1
Column
Address Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh
Counter
www.DataSheet4U.com
Row
Decoder
Memory
Array
Bank 0
8192 x
1024 x
8 Bit
Row
Decoder
Memory
Array
Bank 1
8192 x
1024 x
8 Bit
Row
Decoder
Memory
Array
Bank 2
8192 x
1024 x
8 Bit
Row
Decoder
Memory
Array
Bank 3
8192 x
1024 x
8 Bit
Input Buffer Output Buffer
DQ0 - DQ7
Control Logic & Timing Generator
*) on SSTL versions only
CLK CKE CS RAS CAS WE DQM VREF*)
SPB03780
Block Diagram for 32 M × 8 SDRAM (13/10/2 addressing)
Semiconductor Group
5
1998-10-01
5 Page 
HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner.During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The
power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD supplies. The CLK
signal must be started at the same time. After power on, an initial pause of 200 µs is required
followed by a precharge of both banks using the precharge command. To prevent data contention
on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the
initial pause period. Once all banks have been precharged, the Mode Register Set Command must
be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow
these steps may lead to unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is divided
into 4 fields. A Burst Length field to set the length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency
field to set the access time at clock cycle and a Operation mode field to differentiate between normal
operation (burst read and burst write) and a special burst read and single write mode. The mode set
operationwww.DataSheet4U.com must be done before any activate command after the initial power up. Any content of the
mode register can be altered by re-executing the mode set command. All banks must be in
precharged state and CKE must be high at least one clock before the mode set operation. After the
mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE
at the positive edge of the clock activate the mode set operation. Address input data at this timing
defines parameters to be set as shown in the previous table.
Read and Write Operation
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 143 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organization and column addressing. Full page burst operation do not self
Semiconductor Group
11
1998-10-01
11 Page | ||
| Páginas | Total 56 Páginas | |
| PDF Descargar | [ Datasheet HYB39S256800T.PDF ] | |
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