|
|
PDF HYB39S256400DC Data sheet ( Hoja de datos )
| Número de pieza | HYB39S256400DC | |
| Descripción | (HYB39S256xxxD) 256 MBit Synchronous DRAM | |
| Fabricantes | Infineon Technologies | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HYB39S256400DC (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
256 MBit Synchronous DRAM
• High Performance:
-6 -7 -7.5 -8 Units
fCK 166 143 133 125 MHz
tCK3 6
7 7.5 8
ns
tAC3 5
5.4 5.4
6
ns
tCK2 7.5 7.5 10 10
ns
tAC2 5.4 5.4
6
6
ns
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2 & 3
www.DataSheet4•U.coPmrogrammable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length:
1, 2, 4, 8 and full page
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read / Write control (x4, x8)
• Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Power Down and Clock Suspend Mode
• 8192 refresh cycles / 64 ms (7,8 µs)
• Random Column Address every CLK
( 1-N Rule)
• Single 3.3V +/- 0.3V Power Supply
• LVTTL Interface versions
• Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
• Chipsize Packages:
54 ball TFBGA (12 mm x 8 mm)
• -6 parts for PC166 3-3-3 operation
-7 parts for PC133 2-2-2 operation
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
The HYB39S256400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.14 µm 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply. All 256Mbit components are available in TSOPII-54 and TFBGA-54
packages.
INFINEON Technologies
1
2002-04-23
1 page  
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Pinout for x4, x8 & x16 organised 256M-DRAMs
C olum n Address
C o un ter
C olum n Addresses
A 0 - A 9 , A 1 1 , A P,
BA0, BA1
C olum n Address
B uffer
R ow Addresses
A0 - A12,
BA0, BA1
R ow Address
B u ffe r
R efresh C ounter
www.DataSheet4U.com
Row
D ecoder
Mem ory
A rray
Bank 0
8196
x 2048
x 4 Bit
R ow
Decoder
M em ory
A rray
Bank 1
8192
x 2048
x 4 Bit
Row
D ecoder
M em ory
A rray
Bank 2
8192
x 2048
x 4 Bit
R ow
D ecoder
M em ory
A rray
Bank 3
8192
x 2048
x 4 B it
In p ut B u ffe r O u tp u t B uffe r
DQ0 - DQ3
C ontrol Logic &
Tim ing G enerator
S PB 04127_2
Block Diagram for 64M x 4 SDRAM ( 13 / 11 / 2 addressing)
INFINEON Technologies
5
2002-04-23
5 Page 
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Mode Register Set Table
BA1BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus (Ax)
Operation Mode
CAS Latency BT Burst Length
Mode Register (Mx)
Operation Mode
M9 Mode
0 burst read / burst write
1 burst read / single write
Burst Type
M3 Type
0 Sequential
1 Interleave
www.DataSheet4U.com
CAS Latency
M6 M5 M4
000
001
010
011
100
101
110
111
Latency
Reserved
Reserved
2
3
Reserved
Burst Length
Length
M2 M1 M0
Sequential Interleave
000
1
1
001
2
2
010
4
4
011
8
8
100
1 0 1 Reserved
Reserved
110
1 1 1 Full Page
INFINEON Technologies
11
2002-04-23
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet HYB39S256400DC.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HYB39S256400DC | (HYB39S256xxxD) 256 MBit Synchronous DRAM | Infineon Technologies |
| HYB39S256400DCL | (HYB39S256xxxD) 256 MBit Synchronous DRAM | Infineon Technologies |
| HYB39S256400DT | (HYB39S256xxxD) 256 MBit Synchronous DRAM | Infineon Technologies |
| HYB39S256400DTL | (HYB39S256xxxD) 256 MBit Synchronous DRAM | Infineon Technologies |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |