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PDF W3EG7264S-AD4 Data sheet ( Hoja de datos )
| Número de pieza | W3EG7264S-AD4 | |
| Descripción | 512MB - 2x32Mx72 DDR ECC SDRAM UNBUFFERED | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
W3EG7264S-AD4
-BD4
PRELIMINARY*
512MB – 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL
FEATURES
Double-data-rate architecture
DDR200, DDR266 DDR333
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Dual Rank
Power supply: 2.5V ± 0.2V
200www.DataSheet4U.com pin SO-DIMM package
• Package height options:
AD4: 35.05 mm (1.38”)
BD4: 31.75 mm (1.25”)
DESCRIPTION
The W3EG7264S is a 2x32Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of nine 64Mx8 DDR
SDRAMs stacked in 54 pin TSOP packages mounted on
a 200 pin FR4 substrate. This module is structured as 2
Ranks of 64Mx72 DDR SDRAM.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333@CL=2.5
166MHz
2.5-3-3
DDR266@CL=2
133MHz
2-2-2
DDR266@CL=2.5
133MHz
2.5-3-3
DDR200@CL=2
100MHz
2-2-2
January 2005
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3EG7264S-AD4
-BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
DDR333@CL=2.5 DDR266@CL=2, 2.5 DDR200@CL=2
Parameter
Symbol Conditions
Max Max Max
Operating Current
IDD0 One device bank; Active - Precharge;
2205
2025
2025
(MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address
and control inputs changing once every
two cycles. TRC=TRC(MIN); TCK=TCK
Operating Current
IDD1 One device bank; Active-
2610 2340 2340
Read-Precharge; Burst = 2;
TRC=TRC(MIN);TCK=TCK (MIN); Iout
= 0mA; Address and control inputs
changing once per clock cycle.
Precharge Power-Down IDD2P All device banks idle; Power-down
72
72
72
Standby Current
mode; TCK=TCK(MIN); CKE=(low)
Idle Standby Current
IDD2F CS# = High; All device banks idle;
900
810
810
TCK=TCK(MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
Active Power-Down
IDD3P One device bank active; Power-down
540
450
450
Standby Current
mode; TCK(MIN); CKE=(low)
Active Standby Current IDD3N CS# = High; CKE = High; One
1080 900 900
device bank; Active-Precharge;
TRC=TRAS(MAX); TCK=TCK(MIN); DQ,
DM and DQS inputs changing twice per
clock cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continous burst; One
2655
2250
2250
device bank active;Address andcontrol
inputs changing once per clock cycle;
TCK=TCK(MIN); IOUT = 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continous burst; One
2655
2250
2250
device bank active; Address and control
inputs changing once per clock cycle;
TCK=TCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
Auto Refresh Current
IDD5 TRC=TRC(MIN)
3375 3015 3015
Self Refresh Current
IDD6 CKE ≤ 0.2V
72 72 72
Operating Current
IDD7A Four bank interleaving Reads (BL=4)
4770
4050
4050
with auto precharge with TRC=TRC (MIN);
TCK=TCK(MIN); Address and control
inputs change only during Active Read
or Write commands
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
January 2005
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3EG7264S-AD4
-BD4
PRELIMINARY
ORDERING INFORMATION FOR BD4
Part Number
Speed
Height*
W3EG7264S335BD4
166MHz/333Mbps, CL=2.5
31.75 (1.25")
W3EG7264S262BD4
133MHz/266Mbps, CL=2
31.75 (1.25")
W3EG7264S265BD4
133MHz/266Mbps, CL=2.5
31.75 (1.25")
W3EG7264S202BD4
100MHz/200Mbps, CL=2
31.75 (1.25")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR BD4
3.98 ± 0.1
(0.157 ± 0.004)
2.31
(0.091) REF.
11.40
(0.449)
67.56
(2.666) MAX
4.19
(0.165)
1.80
(0.071)
47.40
(1.866)
6.35
(0.250)
MAX.
31.75
(1.25)
20
(0.787)
3.99
(0.157) MIN.
0.99 ± 0.10
(0.039 ± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
January 2005
Rev. 3
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 13 Páginas | |
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