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PDF W3EG7263S-D3 Data sheet ( Hoja de datos )
| Número de pieza | W3EG7263S-D3 | |
| Descripción | 512MB- 64Mx72 DDR SDRAM REGISTERED | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
W3EG7263S-D3
-JD3
-AJD3
PRELIMINARY*
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL
FEATURES
DESCRIPTION
Double-data-rate architecture
Clock Speeds: 100MHz, 133MHz and 166MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply: VCC: 2.5V ± 0.2V
JEDEC standard 184 pin DIMM package
•www.DataSheet4U.com Package height options:
JD3: 30.48mm (1.20") and
AJD3: 28.70mm (1.13")
The W3EG7263S is a 64Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
component. The module consists of eighteen 64Mx4 DDR
SDRAMs in 66 pin TSOP package mounted on a 184 Pin
FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
This product is under development, is not qualified or characterized and is subject to
change without notice.
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
April 2004
Rev. # 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3EG7263S-D3
-JD3
-AJD3
PRELIMINARY
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C £ TA £ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components and PLL and Register
Rank 1
Symbol Conditions
IDD0 One device bank; Active - Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
IDD1 One device bank; Active-Read-
Precharge Burst = 2; tRC = tRC (MIN);
tCK = tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
IDD2P All device banks idle; Power-down
mode; tCK = tCK (MIN); CKE = (low)
IDD2F CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
IDD3P One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS
(MAX); tCK = tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
IDD4R Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK = tCK (MIN); lOUT = 0mA.
IDD4W Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ,DM and DQS
inputs changing once per clock cycle.
IDD5 tRC = tRC (MIN)
IDD6 CKE £ 0.2V
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control
inputs change only during Active Read
or Write commands.
DDR333@CL=2.5
Max
TBD
DDR266:@CL=2, 2.5
Max
1715
DDR200@CL=2 S
Max
1715
TBD 2255 2255
TBD 54
54
TBD 671 671
TBD 540 540
TBD 1121 1121
TBD 2795 2795
TBD 2795 2795
TBD 3281 3281
TBD 365 365
TBD 5315 5315
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
Rank 2
Standby
State
IDD3N
IDD3N
IDD2P
IDD2F
IDD3P
IDD3N
IDD3N
IDD3N
IDD3N
IDD6
IDD3N
April 2004
Rev. # 2
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
Part Number
W3EG7263S335AJD3
W3EG7263S262AJD3
W3EG7263S263AJD3
W3EG7263S265AJD3
W3EG7263S202AJD3
ORDERING INFORMATION FOR AJD3
Speed
CAS Latency tRCD
166MHz/333Mb/s
2.5
3
133MHz/266Mb/s
2
2
133MHz/266Mb/s
2
3
133MHz/266Mb/s
2.5
3
100MHz/200Mb/s
2
2
W3EG7263S-D3
-JD3
-AJD3
PRELIMINARY
tRP Height*
3 28.70 (1.13")
2 28.70 (1.13")
3 28.70 (1.13")
3 28.70 (1.13")
2 28.70 (1.13")
PACKAGE DIMENSIONS FOR AJD3
3.99
(0.157 (2x))
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
64.77
(2.550)
6.35
(0.250)
1.78
(0.070)
4.06
(0.160 MAX)
1.27
49.53 (0.050 TYP.)
(1.950)
3.99
28.70
(0.157)
(1.13 MAX) (MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
April 2004
Rev. # 2
* All Dimensions are in millimeters and (inches).
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet W3EG7263S-D3.PDF ] | |
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