PDF W3EG6465S-D3 Data sheet ( Hoja de datos )

Número de pieza	W3EG6465S-D3
Descripción	512MB - 64Mx64 DDR SDRAM UNBUFFERED
Fabricantes	White Electronic
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No Preview Available ! White Electronic Designs W3EG6465S-D3 PRELIMINARY* 512MB – 64Mx64 DDR SDRAM UNBUFFERED FEATURES Double-date-rate architecture DDR200 and DDR266 • JEDEC design speciﬁcation Bi-directional data strobes (DQS) Differential clock inputs (CK CK#) Programmable Read Latency 2, 2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interactive) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detected Power supply: 2.5V ± 0.20V standard 184 pin DIMM package • Package height option: www.DataSheet4U.com D3: 30.48mm (1.20") DESCRIPTION The W3EDG6465S is a 64Mx64 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM components. The module consists of sixteen 64Mx4 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualiﬁed or characterized and is subject to change without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option Clock Speed CL-tRCD-tRP OPERATING FREQUENCIES DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-3-3 DDR200 @CL=2 100MHz 2-2-2 November 2005 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs W3EG6465S-D3 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Operating Current Symbol IDD0 Operating Current IDD1 Precharge Power- Down Standby Current Idle Standby Current IDD2P IDD2F Active Power-Down Standby Current Active Standby Current IDD3P IDD3N Operating Current IDD4R Operating Current IDD4W Auto Refresh Current Self Refresh Current IDD5 IDD6 Operating Current IDD7A Conditions One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-Down mode; tCK (MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active- Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE ≤ 0.2V Standard Low Power Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. DDR266@CL=2 DDR266@CL=2/2.5 DDR200@CL=2 Max Max Max 1280 1280 1280 1600 1600 1600 48 48 48 320 320 320 480 480 480 720 720 720 1920 1920 1920 2160 2160 2160 2560 2560 2560 48 48 48 25 25 25 3840 3840 3840 Units mA mA rnA mA mA mA mA rnA mA mA mA November 2005 Rev. 2 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs Document Title 512MB - 64Mx64, DDR SDRAM UNBUFFERED Revision History Rev # Rev A Rev 0 Rev 1 Rev 2 History Created 0.1 Updated CAP and IDD specs 0.2 Removed "ED" from part marking 0.3 Moved status from Advanced to Preliminary 1.1 Added lead-free and RoHS notes 1.2 Added vendor source control notes 1.3 Added industrial temp notes 1.4 Added AC specs 2.1 Updated RoHS notes 2.2 Correction to IDD spec W3EG6465S-D3 PRELIMINARY Release Date Status 9-23-02 Advanced 6-04 Preliminary 12-04 Preliminary 11-05 Preliminary November 2005 Rev. 2 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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