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PDF X9525 Data sheet ( Hoja de datos )
| Número de pieza | X9525 | |
| Descripción | EEPROM Memory | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X9525 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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X9525NOTPRXO9ES5CS8O2IBM0L,MEISESLN2UD2BE3S2®DT6FI,TIOSURLT2END2EFP3aWi2Rtb9aOe,DrDSXECUh9S5heCI2GaeT0ntNnSel/Gigabit
Ethernet
Laser Diode Control
January 3, 2006
for
Fiber
Optic Modules
FN8210.1
Dual DCP, EEPROM Memory
FEATURES
• Two Digitally Controlled Potentiometers (DCP’s)
—100 Tap - 10kΩ
—256 Tap - 50kΩ
— Non-Volatile
—Write Protect Function
• 2kbit EEPROM Memory with Write Protect & Block
LockTM
• Device ID Addressability
• 2-Wire Industry Standard Serial Interface
—Complies to the Gigabit Interface Converter
(GBIC) specification
— Addressable
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• Package
—20 Pin TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9525 combines two Digitally Controlled Potentiom-
eters (DCP’s), and integrated EEPROM with Block
Lock™ protection. All functions of the X9525 are
accessed by an industry standard 2-Wire serial interface.
The DCP’s of the X9525 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The 2kbit integrated EEPROM may be
used to store module definition data.
The features of the X9525 are ideally suited to simplifying
the design of fiber optic modules which comply to the Gi-
gabit Interface Converter (GBIC) specification. The inte-
gration of these functions into one package significantly
reduces board area, cost and increases reliability of laser
diode modules.
BLOCK DIAGRAM
www.DataSheet4U.com
WP
SDA
SCL
Ao
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
THRESHOLD
RESET LOGIC
8
PROTECT
LOGIC
CONSTAT
REGISTER
4
2kbit
EEPROM
ARRAY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
RH1
RW1
RL1
RH2
RW2
RL2
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
©2001 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X9525
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9525
initiates an internal high voltage write cycle. This cycle
typically requires 5 ms. During this time, no further Read
or Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no ACKNOWL-
EDGE will be returned. If the device has completed the
write operation, an ACKNOWLEDGE will be returned
and the host can then proceed with a read or write opera-
tion. (Refer to Figure 5.).
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
ACK
returned?
YES
High Voltage Cycle
complete. Continue
command sequence?
NO
NO
YES
Continue normal
Read or Write
command sequence
Issue STOP
PROCEED
N RHx
WIPER
COUNTER
REGISTER
(WCR)
NON
VOLATILE
MEMORY
(NVM)
DECODER
2
1
0
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
Figure 6. DCP Internal Structure
RLx
RWx
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9525 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RHx and RLx
inputs - where x = 1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(Rwx) output. Within each individual array, only one
switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.
On power-up of the X9525, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The intial values of the
DCP WCR’s (before the contents of the NVM is loaded
into the WCR) are 0 and 255 for DCP1 (100 tap) and
DCP2 (256 tap) respectively. The data in the WCR is
then decoded to select and enable one of the respective
FET switches. A “make before break” sequence is used
internally for the FET switches when the wiper is moved
from one tap position to another.
Figure 5. Acknowledge Polling Sequence
5 FN8210.1
January 3, 2006
5 Page 
X9525
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
WRITE Operation S
Address
Byte
t
a
r
t
Slave
Address
READ Operation
S
t
o
p
10 1 0 0A0 0 0 0
A
C
K
1 0 1 0 0A0 0 0 1
AA
CC
KK
Data
“Dummy” Write
Figure 15. Random EEPROM Address Read Sequence
Random EEPROM Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
issues the START condition and the Slave Address Byte,
receives an ACKNOWLEDGE, then issues an Address
Byte. This “dummy” Write operation sets the address
pointer to the address from which to begin the random
EEPROM read operation.
After the X9525 acknowledges the receipt of the Address
Byte, the master immediately issues another START
condition and the Slave Address Byte with the R/W bit
set to one. This is followed by an ACKNOWLEDGE from
the X9525 and then by the eight bit word. The master ter-
minates the read operation by not responding with an
ACKNOWLEDGE and instead issuing a STOP condition
(Refer to Figure 15.).
A similar operation called “Set Current Address” also
exists. This operation is performed if a STOP is issued
instead of the second START shown in Figure 15. In this
case, the device sets the address pointer to that of the
Address Byte, and then goes into standby mode after the
STOP bit. All bus activity will be ignored until another
START is detected.
Sequential EEPROM Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an ACKNOWLEDGE,
indicating it requires additional data. The X9525 contin-
ues to output a Data Byte for each ACKNOWLEDGE
received. The master terminates the read operation by
not responding with an ACKNOWLEDGE and instead
issuing a STOP condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
the entire memory contents to be serially read during
one operation. At the end of the address space the
counter “rolls over” to address 00h and the device con-
tinues to output data for each ACKNOWLEDGE
received (Refer to Figure 16.).
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
AAA
Address
C
K
C
K
C
K
A00 0 0 1
A
C
K
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
Figure 16. Sequential EEPROM Read Sequence
S
t
o
p
11 FN8210.1
January 3, 2006
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet X9525.PDF ] | |
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