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PDF X9522 Data sheet ( Hoja de datos )
| Número de pieza | X9522 | |
| Descripción | Dual Voltage Monitors | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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X9522
Laser Diode Control for Fiber Optic Modules
January 3, 2006
FN8208.1
Triple DCP, Dual Voltage Monitors
FEATURES
• Three Digitally Controlled Potentiometers (DCPs)
—64 Tap - 10kΩ
—100 Tap - 10kΩ
—256 Tap - 100kΩ
— Nonvolatile
—Write Protect Function
• 2-Wire industry standard Serial Interface
• Dual Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• 20 Pin package
— TSSOP
DESCRIPTION
The X9522 combines three Digitally Controlled Potenti-
ometers (DCPs), and two programmable voltage monitor
inputs with software and hardware indicators. All func-
tions of the X9522 are accessed by an industry standard
2-Wire serial interface.
Two of the DCPs of the X9522 may be utilized to control
the bias and modulation currents of the laser diode in a
Fiber Optic module. The third DCP may be used to set
other various reference quantities, or as a coarse trim for
one of the other two DCPs.The programmable voltage
monitors may be used for monitoring various module
alarm levels.
The features of the X9522 are ideally suited to simplifying
the design of fiber optic modules. The integration of
these functions into one package significantly reduces
board area, cost and increases reliability of laser diode
modules.
BLOCK DIAGRAM
www.DataSheet4U.com
WP
SDA
SCL
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
THRESHOLD
RESET LOGIC
V3
V2
Vcc / V1
8
PROTECT LOGIC
CONSTAT
REGISTER
VTRIP3
VTRIP 2
-
+
-
+
2
WIPER
COUNTER
REGISTER
6 - BIT
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
7 - BIT
NONVOLATILE
MEMOR Y
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMOR Y
RH0
RW0
RL0
RH1
RW1
RL1
RH2
RW2
RL2
V3RO
V2RO
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X9522
SCL
from
Master
Data Output
from
Transmitter
1
89
Data Output
from
Receiver
Start
Acknowledge
Figure 3. Acknowledge Response From Receiver
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9522
can be split up into two main parts:
—Three Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte proto-
col is used. All operations however must begin with
the Slave Address Byte being issued on the SDA pin.
The Slave address selects the part of the X9522 to
be addressed, and specifies if a Read or Write opera-
tion is to be performed.
It should be noted that in order to perform a write opera-
tion to a DCP, the Write Enable Latch (WEL) bit must first
be set.
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9522.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally
selects the DCP structures in the X9522. The CON-
STAT Register may be selected using the Internal
Device Address 010.All other bit combinations are
RESERVED.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
101 0
R/W
DEVICE TYPE
IDENTIFIER
Internal Address
(SA3 - SA1)
010
111
Others
INTERNAL
DEVICE
ADDRESS
READ /
WRITE
Internally Addressed
Device
CONSTAT Register
DCP
RESERVED
Bit SA0
0
1
Operation
WRITE
READ
Figure 4. Slave Address Format
5 FN8208.1
January 3, 2006
5 Page 
X9522
SCL
SDA
S 1 0 1 0 0 1 0 R/W A 1
TC
AK
R
T
SLAVE ADDRESS BYTE
1 11 1 1 1 1
ADDRESS BYTE
A CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 A S
C CT
K KO
CONSTAT REGISTER DATA IN
P
Figure 12. CONSTAT Register Write Command Sequence
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT regis-
ter requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the DWLK bit. The
X9522 will not ACKNOWLEDGE any data bytes written
after the first byte is entered (Refer to Figure 12.).
When writing to the CONSTAT register, the bits CS7,
CS4 and CS0 must all be set to “0”. Writing any other bit
sequence to bits CS7, CS4 and CS0 of the CONSTAT
register is reserved.
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps:
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
—Write a 06H to the CONSTAT Register to set the
Register Write Enable Latch (RWEL) AND the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceded by a START
and ended with a STOP).
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as 0xy0t010 in binary,
where xy are the Voltage Monitor Output Status
(V2OS and V3OS) bits, and t is the DCP Write Lock
(DWLK) bit. This operation is proceeded by a START
and ended with a STOP bit. Since this is a nonvolatile
write cycle, it will typically take 5ms to complete. The
RWEL bit is reset by this cycle and the sequence must
be repeated to change the nonvolatile bits again. If bit
2 is set to ‘1’ in this third step (0xy0 t110) then the
RWEL bit is set, but the DWLK bit will remain
unchanged. Writing a second byte to the control regis-
ter is not allowed. Doing so aborts the write operation
and the X9522 does not return an ACKNOWLEDGE.
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset the
nonvolatile (DWLK) bit in the CONSTAT Register to “0”.
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
WRITE Operation
Address
Byte
10 1 0 0 1 0 0
S
t
a Slave
r Address
t
READ Operation
CS7 … CS0
10 1 0 0 101
AA
CC
KK
A
C
K
Data
S
t
o
p
“Dummy” Write
Figure 13. CONSTAT Register Read Command Sequence
11 FN8208.1
January 3, 2006
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet X9522.PDF ] | |
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