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PDF X9250 Data sheet ( Hoja de datos )
| Número de pieza | X9250 | |
| Descripción | Quad Digitally Controlled Potentiometers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
X9250
Low Noise/Low Power/SPI Bus/256 Taps
August 29, 2006
FN8165.3
Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Four potentiometers in one package
• 256 resistor taps/pot - 0.4% resolution
• SPI serial interface
• Wiper resistance, 40Ω typical @ VCC = 5V
• Four nonvolatile data registers for each pot
• Nonvolatile storage of wiper position
• Standby current < 5µA max (total package)
• Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• 100kΩ, 50kΩ total pot resistance
• High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention - 100 years
• 24 Ld SOIC, 24 Ld TSSOP
• Dual supply version of X9251
• Pb-free plus anneal available (RoHS compliant)
www.DataSheet4U.com
DESCRIPTION
The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array though the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V-
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
8
Data
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Pot 0
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW1/RW1
Resistor
Array
Pot1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VW3/RW3
VH3/RH3
VL3/RH3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X9250
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
Register 0
Register 1
88
Serial
Bus
Input
Parallel
Bus
Input
C
o
u
n
t
e
r
Register 2
If WCR = 00[H] then VW/RW = VL/RL
If WCR = FF[H] then VW/RW = VH/RH
Register 3
Wiper
Counter
Register
(WCR)
UP/DN
Modified SCK
Inc/Dec
Logic
UP/DN
CLK
D
e
c
o
d
e
VH/RH
VL/RL
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0 - A1 input
pins. The X9250 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9250 to successfully
continue the command sequence. The A0 - A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
VW/RW
Figure 2. Identification Byte Format
Device Type
Identifier
0 1 0 1 0 0 A1 A0
Device Address
Instruction Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
Figure 3. Instruction Byte Format
Register
Select
I3 I2 I1 I0 R1 R0 P1 P0
Instructions
Pot Select
5 FN8165.3
August 29, 2006
5 Page 
X9250
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ........................ -65 to +135°C
Storage temperature ............................. -65 to +150°C
Voltage on SCK, SCL or any address input
with respect to VSS ................................. -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) .............................................................. 12V
Any VH/RH ..............................................................V+
Any VL/RL.................................................................V-
Lead temperature (soldering, 10s) .................. +300°C
IW (10s) ............................................................±15mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Device
X9250
X9250-2.7
Supply Voltage (VCC) Limits(4)
5V ±10%
2.7V to 5.5V
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min.
Limits
Typ. Max.
Unit
Test Conditions
IW
RW
Vv+
Vv-
VTERM
CH/CL/CW
End to end resistance tolerance
Power rating
Wiper current
Wiper resistance
Voltage on V+ pin
X9250
X9250-2.7
Voltage on V- pin
X9250
X9250-2.7
Voltage on any VH/RH or VL/RL pin
Noise
Resolution (4)
Absolute linearity (1)
Relative linearity (2)
Temperature coefficient of RTOTAL
Ratiometric Temperature
Coefficient
Potentiometer Capacitances
+4.5
+2.7
-5.5
-5.5
V-
150
-120
0.6
±300
10/10/25
±20
50
±7.5
250
+5.5
+5.5
-4.5
-2.7
V+
±1
±0.6
±20
%
mW +25°C, each pot
mA
Ω Wiper current = ± 1mA
V
V
V
dBV
%
MI(3)
MI(3)
ppm/°C
ppm/°C
Ref: 1kHz
Vw(n)(actual) - Vw(n)(expected)
Vw(n + 1 - [Vw(n) + MI]
pF See Circuit #3
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/255 or (VH/RH - VL/RL)/255, single pot
(4) Individual array resolutions.
11 FN8165.3
August 29, 2006
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet X9250.PDF ] | |
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