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PDF X5083 Data sheet ( Hoja de datos )
| Número de pieza | X5083 | |
| Descripción | CPU Supervisor | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
June 15, 2006
X5083
FN8127.3
CPU Supervisor with 8Kbit SPI EEPROM
This device combines four popular functions, Power-on Reset
Control, Watchdog Timer, Supply Voltage Supervision, and
Block Lock Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET active for a period of time. This
allows the power supply and oscillator to stabilize before the
processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller fails to
restart a timer within a selectable time out interval, the device
activates the RESET signal. The user selects the interval
from three preset values. Once selected, the interval does
not change, even after cycling the power.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point. RESET is
asserted until VCC returns to the proper operating level and
stabilizes. Five industry standard VTRIP thresholds are
www.DataSheet4U.coamvailable, however, Intersil’s unique circuits allow the threshold
to be reprogrammed to meet custom requirements or to fine-
tune the threshold for applications requiring higher precision.
Pinouts
8 LD TSSOP
RESET
VCC
CS/WDI
SO
18
2
3
X5083
7
6
45
SCK
SI
VSS
WP
8 LD SOIC, 8 LD PDIP
CS/WDI
SO
WP
VSS
18
27
3 X5083 6
45
VCC
RESET
SCK
SI
Features
• Low VCC detection and reset assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low VCC reset threshold voltage using
special programming sequence
- Reset signal valid to VCC = 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lock™ memory
- Block lock first or last page, any 1/4 or lower 1/2 of
EEPROM array
• Built-in inadvertent write protection
- Write enable latch
- Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
- 16 byte page write mode
- 5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
Applications
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X5083
Principles of Operation
Power-on Reset
Application of power to the X5083 activates a power-on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. RESET
active also blocks communication to the device through the
SPI interface. When VCC exceeds the device VTRIP value for
200ms (nominal) the circuit releases RESET, allowing the
processor to begin executing code. While VCC < VTRIP
communications to the device are inhibited.
Low Voltage Monitoring
During operation, the X5083 monitors the VCC level and
asserts RESET if supply voltage falls below a preset
minimum VTRIP. The RESET signal prevents the
microprocessor from operating in a power fail or brownout
condition and terminates any SPI communication in
progress. The RESET signal remains active until the voltage
drops below 1V. It also remains active until VCC returns and
exceeds VTRIP for 200ms.
When VCC falls below VTRIP, any communications in
progress are terminated and communications are inhibited
until VCC exceeds VTRIP for tPURST.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the WDI input. The microprocessor must toggle
the CS/WDI pin periodically to prevent a RESET signal. The
CS/WDI pin must be toggled from HIGH to LOW prior to the
expiration of the watchdog time out period. The state of two
nonvolatile control bits in the status register determine the
watchdog timer period. The microprocessor can change these
watchdog bits with no action taken by the microprocessor
these bits remain unchanged, even after total power failure.
VCC Threshold Reset Procedure
The X5083 is shipped with a standard VCC threshold (VTRIP)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard VTRIP is not exactly right, or if higher precision is
needed in the VTRIP value, the X5083 threshold may be
adjusted. The procedure is described below, and uses the
application of a high voltage control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and the new
VTRIP is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it
is necessary to reset the trip point before setting the new
value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to the
programming voltage VP. Then send a WREN command,
followed by a write of Data 00h to address 01h. CS going
HIGH on the write operation initiates the VTRIP programming
sequence. Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address 01h.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the new
VTRIP must be 4.0V, then the VTRIP must be reset. When
VTRIP is reset, the new VTRIP is something less than 1.7V.
This procedure must be used to set the voltage to a lower
value.
To reset the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the Vcc pin and tie the WP pin to the
programming voltage VP. Then send a WREN command,
followed by a write of data 00h to address 03h. CS going
HIGH on the write operation initiates the VTRIP programming
sequence. Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address 03h.
5 FN8127.3
June 15, 2006
5 Page 
X5083
CS
SCK
SI
01234567
Instruction
(1 Byte)
SO High Impedance
FIGURE 7. WREN/WRDI SEQUENCE
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16 Bit Address
Data Byte 1
15 14 13
3 2 10 7 65 43 2 10
CS
SCK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Data Byte N
654 321 0
FIGURE 8. EEPROM ARRAY WRITE SEQUENCE
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
SO High Impedance
Data Byte
6 54 3 2 1 0
W
D1
W
D
0
BL
2
B
L
1
B
L
0
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
11
FN8127.3
June 15, 2006
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet X5083.PDF ] | |
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