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PDF FMS6410B Data sheet ( Hoja de datos )
| Número de pieza | FMS6410B | |
| Descripción | Dual-Channel Video Drivers | |
| Fabricantes | Fairchild Semiconductor | |
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October 2006
FMS6410B
Dual-Channel Video Drivers with Integrated Filters and
Composite Video Summer
Features
■ 7.1MHz fifth-order Y,C filters with composite summer
■ 50dB stopband attenuation at 27MHz on Y, C, and CV
outputs
■ Better than 0.1dB flatness to 4.5MHz on Y, C, and CV
outputs
■ No external frequency selection components or clocks
■ < 5ns group delay on Y, C, and CV outputs
■ AC-coupled inputs
■ AC- or DC-coupled outputs
■ Capable of PAL frequency selection components or
clocks
■ 0.3% differential gain with 0.2° differential phase on
Y, C, and CV channels
■ Integrated DC restore circuitry with low tilt
■ Lead-free SOIC-8 package
Applications
■ Cable and satellite set-top boxes
■ DVD players
■ Personal Video Recorders (PVR)
■ Video On Demand (VOD)
Description
The FMS6410B is a dual Y/C fifth-order Butterworth low-
pass video filter optimized for minimum overshoot and
flat group delay. The device also contains a summing cir-
cuit to generate filtered composite video. In a typical
application, the Y and C input signals from DACs are AC
coupled into the filters. Both channels have DC restore
circuitry to clamp the DC input levels during video sync.
The Y and C channels use separate feedback clamps.
The clamp pulse is derived from the Y channel.
All outputs are capable of driving 2Vpp, AC or DC cou-
pled, into either a single or dual video load. A single
video load consists of a series 75Ω impedance matching
resistor connected to a terminated 75Ω line. This pre-
sents a total of 150Ω of loading to the part. A dual load is
two of these in parallel, which presents a total of 75Ω to
the part. The gain of the Y, C, and CV signals is 6dB with
1Vpp input levels. All video channels are clamped during
sync to establish the appropriate output voltage refer-
ence levels.
Block Diagrams
YIN 1
Sync Strip
Reference and
Timing
VCC
7
6dB
8 YOUT
CIN 4
© 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
gM
250mV
gM
250mV
+
Σ
+
6dB
3
GND
Figure 1. Block Diagram
6 CVOUT
5 COUT
www.fairchildsemi.com
1 page  
Applications Information
Functional Description
This product is a two-channel, monolithic, continuous-
time, video filter designed for reconstructing the lumi-
nance and chrominance signals from an S-Video D/A
source. Composite video output is generated by sum-
ming the Y and C outputs. The chip is designed to have
AC-coupled inputs and work with either AC- or DC-cou-
pled outputs.
The reconstruction filters provide a fifth-order Butter-
worth response with group delay equalization. This pro-
vides a maximally flat response in terms of delay and
amplitude. Each of the three outputs is capable of driving
2Vpp into a 75Ω load.
All channels are clamped during the sync interval to set
the appropriate minimum output DC level. With this oper-
ation, the effective input time constant is greatly reduced,
which allows use of small, low-cost coupling capacitors.
The net effect is that the input settles to 10mV in 10ms
for any DC shifts present in the input video signal.
In most applications, the input coupling capacitors are
0.1µF. The Y and C inputs typically sink 1µA of current
during active video, which normally tilts a horizontal line
by 2mV at the Y output. During sync, the clamp restores
this leakage current by sourcing an average of 20µA
over the clamp interval. Any change in the coupling
capacitor values affect the amount of tilt per line. Any
reduction in tilt comes with an increase in settling time.
Luminance (Y) I/O
The typical luma input is driven by either a low-imped-
ance source of 1Vpp or the output of a 75Ω terminated
line driven by the output of a current DAC. In either case,
the input must be capacitively coupled to allow the sync-
detect and DC-restore circuitry to operate properly.
All outputs are capable of driving 2Vpp, AC or DC cou-
pled, into either a single or dual video load. A single
video load consists of a series 75Ω impedance matching
resistor connected to a terminated 75Ω line, presenting a
total of 150Ω of loading to the part. A dual load is two of
these in parallel, which presents a total of 75Ω to the
part. The gain of the Y, C, and CV signals is 6dB with
1Vpp input levels.
Chrominance (C) I/O
The chrominance input can be driven in the same man-
ner as the luminance input, but is typically only a 0.7Vpp
signal.
Since the chrominance signal doesn't contain any DC
content, the output signal can be AC coupled using a
capacitor as small as 0.1µF if DC coupling is not desired.
Composite Video (CV) Output
The composite video output driver is same as the other
outputs.
Layout Considerations
General layout and supply bypassing play major roles in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board,
FMS6410BDEMO, to guide layout and aid device testing
and characterization. The FMS6410BDEMO is a four-
layer board with a full power and ground plane. For opti-
mum results, follow the steps below as a basis for high-
frequency layout:
■ Include 10μF and 0.1μF ceramic bypass capacitors.
■ Place the 10μF capacitor within 0.75 inches of the
power pin.
■ Place the 0.1μF capacitor within 0.1 inches of the
power pin.
■ If using DC-coupled outputs, use a large ground plane
to help dissipate heat.
■ Minimize all trace lengths to reduce series induc-
tances.
Output Interface
To obtain the highest quality output signal, place the
series termination resistor as close to the device output
pin as possible. This greatly reduces the parasitic
capacitance and inductance effect on the output of the
driver. Place the series termination resistor less than 0.1
inches from the device pin, as shown in Figure 4.
Figure 4. 75Ω Series Resistor 0.1 Inches from Pin
Figure 5 is the schematic representation of a video filter/
driver used in a system as the output driver to a media
device. In this case, the composite video signal is termi-
nated by the media device and the S-video output termi-
nations are open. It is very critical to have the series
termination resistors close to the output pins of the
device to minimize the effects of parasitic capacitance on
the filter output driver which may show up as noise on
the CV output.
© 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
5
www.fairchildsemi.com
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| PDF Descargar | [ Datasheet FMS6410B.PDF ] | |
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