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PDF X4163 Data sheet ( Hoja de datos )
| Número de pieza | X4163 | |
| Descripción | (X4163 / X4165) CPU Supervisor | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
April 13, 2005
X4163, X4165
16K, 2K x 8 Bit
FN8120.0
CPU Supervisor with 16K EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 16Kbits of EEPROM
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block Lock (1, 2, 4, 8 pages, all, none)
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available Packages
www.DataSheet4U.com — 8-lead SOIC
—8-lead TSSOP
BLOCK DIAGRAM
DESCRIPTION
The X4163/5 combines four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the set minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Four industry
standard VTRIP thresholds are available, however, Inter-
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
WP
SDA
SCL
S0
S1
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
EEPROM Array
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET (X4163)
RESET (X4165)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
Figure 4. VTRIP Programming Sequence
X4163, X4165
New VCC Applied =
Old VCC Applied + Error
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
Execute
Set VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 50mV)
New VCC Applied =
Old VCC Applied - Error
Execute
Reset VTRIP
Sequence
NO RESET pin
goes active?
YES
Error ≤ –Emax
Emax = Maximum Allowed VTRIP Error
Measured VTRIP -
Desired VTRIP
Error ≥ Emax
–Emax < Error < Emax
DONE
Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, and WD0. The X4163/5 will not acknowledge
any data bytes written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X4163/5 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
7 6 5 43 2 10
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
5 FN8120.0
April 13, 2005
5 Page 
X4163, X4165
Figure 12. Current Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
Slave
Address
101 0
1
A
C
K
Data
S
t
o
p
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 12
for the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 13. Random Address Read Sequence
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a
stop is issued instead of the second start shown in Fig-
ure 13. The device goes into standby mode after the
stop and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a Slave
r Address
t
Word Address
Byte 1
Word Address
Byte 0
S
t
a
r
t
101 0
0
AAA
CCC
KKK
Slave
Address
1
A
C
K
Data
S
t
o
p
11 FN8120.0
April 13, 2005
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet X4163.PDF ] | |
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