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PDF XB1009-BD Data sheet ( Hoja de datos )
| Número de pieza | XB1009-BD | |
| Descripción | GaAs MMIC Buffer Amplifier | |
| Fabricantes | Mimix Broadband | |
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14.0-30.0 GHz GaAs MMIC
Buffer Amplifier
February 2007 - Rev 05-Feb-07
Features
Excellent Transmit LO/Output Buffer Stage
On-Chip ESD Protection
18.0 dB Small Signal Gain
+22.0 dBm P1dB Compression Point
100% On-Wafer RF, DC and Output Power Testing
100% Visual Inspection to MIL-STD-883 Method 2010
B1009-BD
Chip Device Layout
General Description
Mimix Broadband’s three stage 14.0-30.0 GHz GaAs
MMIC buffer amplifier has a small signal gain of 18.0
dB with a +22.0 dBm P1dB output compression point.
This MMIC uses Mimix Broadband’s 0.15 µm GaAs
PHEMT device model technology, and is based upon
electron beam lithography to ensure high
repeatability and uniformity.The chip has surface
passivation to protect and provide a rugged part with
backside via holes and gold metallization to allow
either a conductive epoxy or eutectic solder die
attach process.This device is well suited for
www.DataSheet4U.com
Millimeter-wave Point-to-Point Radio, LMDS, SATCOM
and VSAT applications.
Absolute Maximum Ratings
Supply Voltage (Vd)
Supply Current (Id1,2)
Gate Bias Voltage (Vg)
Input Power (Pin)
Storage Temperature (Tstg)
Operating Temperature (Ta)
Channel Temperature (Tch)
+6.0 VDC
110, 340 mA
+0.3 VDC
+12.0 dBm
-65 to +165 OC
-55 to MTTF Graph1
MTTF Graph1
(1) Channel temperature affects a device's MTTF. It is
recommended to keep channel temperature as low as
possible for maximum life.
Electrical Characteristics (Ambient Temperature T = 25 oC)
Parameter
Frequency Range (f )
Input Return Loss (S11)
Output Return Loss (S22)
Small Signal Gain (S21)
Gain Flatness ( S21)
Reverse Isolation (S12)
Output Power for 1dB Compression (P1dB) 2
Drain Bias Voltage (Vd1,2)
Gate Bias Voltage (Vg1,2)
Supply Current (Id1) (Vd=5.0V, Vg=-0.6V Typical)
Supply Current (Id2) (Vd=5.0V, Vg=-0.6V Typical)
(2) Measured using constant current.
Units Min. Typ. Max.
GHz 14.0 - 30.0
dB - 7.0 -
dB - 8.0 -
dB - 18.0 -
dB - +/-4.0 -
dB - 40.0 -
dBm - +22.0 -
VDC - +5.0 +5.5
VDC -1.0 -0.6 0.0
mA - 80 95
mA - 240 290
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com
Page 1 of 7
Characteristic Data and Specifications are subject to change without notice. ©2007 Mimix Broadband, Inc.
Export of this item may require appropriate export licensing from the U.S. Government. In purchasing these parts, U.S. Domestic customers accept
their obligation to be compliant with U.S. Export Laws.
1 page  
14.0-30.0 GHz GaAs MMIC
Buffer Amplifier
February 2007 - Rev 05-Feb-07
B1009-BD
App Note [1] Biasing - It is recommended to separately bias each amplifier stage Vd1 through Vd2 at Vd(1,2)=5.0V with Id1=80 mA and
Id2=240 mA. Separate biasing is recommended if the amplifier is to be used at high levels of saturation, where gate rectification will alter the
effective gate control voltage. For non-critical applications it is possible to parallel all stages and adjust the common gate voltage for a total drain
current Id(total)=320 mA. It is also recommended to use active biasing to keep the currents constant as the RF power and temperature vary; this
gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias circuit may be a
single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to sense the current.The gate of
the pHEMT is controlled to maintain correct drain current and thus drain voltage.The typical gate voltage needed to do this is -0.6V.Typically the
gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative gate bias is
available before applying the positive drain supply.
App Note [2] Bias Arrangement -
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC bypass
capacitors (~100-200 pF) can be combined. Additional DC bypass capacitance (~0.01 uF) is also recommended to all DC or combination (if gate or
drains are tied together) of DC bias pads.
For Individual Stage Bias (Recommended for saturated applications) -- Each DC pad (Vd1,2 and Vg1,2) needs to have DC bypass capacitance
(~100-200 pF) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended.
MTTF Graphs
These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.
1.0E+10
XB1009-BD Vd1,2=5.0 V Id1,2=320 mA
1.0E+05
XB1009-BD Vd1,2=5.0 V Id1,2=320 mA
1.0E+09
1.0E+08
1.0E+07
1.0E+06
1.0E+05
1.0E+04
1.0E+03
1.0E+02
1.0E+01
1.0E+04
55 65 75 85 95 105 115 125
Backplate Temperature (deg C)
No RF
Pout=+21 dBm
1.0E+00
55 65 75 85 95 105 115 125
Backplate Temperature (deg C)
No RF
Pout=+21 dBm
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
55
XB1009-BD Vd1,2=5.0 V Id1,2=320 mA
65 75 85 95 105 115 125
Backplate Temperature (deg C)
No RF
Pout=+21 dBm
250
230
210
190
170
150
130
55
XB1009-BD Vd1,2=5.0 V Id1,2=320 mA
65 75 85 95 105 115 125
Backplate Temperature (deg C)
No RF
Pout=+21 dBm
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com
Page 5 of 7
Characteristic Data and Specifications are subject to change without notice. ©2007 Mimix Broadband, Inc.
Export of this item may require appropriate export licensing from the U.S. Government. In purchasing these parts, U.S. Domestic customers accept
their obligation to be compliant with U.S. Export Laws.
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet XB1009-BD.PDF ] | |
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