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PDF LAN9115 Data sheet ( Hoja de datos )
| Número de pieza | LAN9115 | |
| Descripción | Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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LAN9115
Highly Efficient Single-
Chip 10/100 Non-PCI
Ethernet Controller
PRODUCT FEATURES
Datasheet
Highlights
■ Member of LAN9118 Family; optimized for medium-
performance applications
■ Easily interfaces to most 16-bit embedded CPU’s
■ Efficient architecture with low CPU overhead
■ Integrated PHY; supports external PHY via MII
interface
■ Supports audio & video streaming over Ethernet:
multiple standard-definition (SD) MPEG2 streams
■ Medium-speed member of LAN9118 Family
(all members are pin-compatible)
Target Applications
■ Printers, kiosks, security systems
■ General embedded applications
■ Audio distribution systems
■ Basic Cable, satellite, and IP set-top boxes
■ Video-over IP Solutions, IP PBX & Video Phones
■ Wireless routers & access points
■ Digital video recorders
Key Benefits
■ Non-PCI Ethernet controller for medium-performance
applications
— 16-bit interface
— Burst-mode read support
— External MII Interface
■ Eliminates dropped packets
— Internal SRAM can store over 200 packets
— Supports automatic or host-triggered PAUSE and back-
pressure flow control
■ Minimizes CPU overhead
— Supports Slave-DMA
— Interrupt Pin with Programmable Hold-off timer
■ Reduces system cost and increases design flexibility
— SRAM-like interface easily interfaces to most
Embedded CPU’s or SoC’s
— Low-cost, low--pin count non-PCI interface for
embedded designs
■ Reduced Power Modes
— Numerous power management modes
— Wake on LAN*
— Magic packet wakeup*
— Wakeup indicator event signal
— Link Status Change
■ Single chip Ethernet controller
— Fully compliant with IEEE 802.3/802.3u standards
— Integrated Ethernet MAC and PHY
— 10BASE-T and 100BASE-TX support
— Full- and Half-duplex support
— Full-duplex flow control
— Backpressure for half-duplex flow control
— Preamble generation and removal
— Automatic 32-bit CRC generation and checking
— Automatic payload padding and pad removal
— Loop-back modes
■ Flexible address filtering modes
— One 48-bit perfect address
— 64 hash-filtered multicast addresses
— Pass all multicast
— Promiscuous mode
— Inverse filtering
— Pass all incoming with status report
— Disable reception of broadcast packets
■ Integrated Ethernet PHY
— Auto-negotiation
— Automatic polarity detection and correction
■ High-Performance host bus interface
— Simple, SRAM-like interface
— 16-bit data bus
— Large, 16Kbyte FIFO memory that can be allocated to
RX or TX functions
— One configurable host interrupt
■ Miscellaneous features
— Low profile 100-pin TQFP package; green, lead free
package also availaible
— Integral 1.8V regulator
— General Purpose Timer
— Support for optional EEPROM
— Support for 3 status LEDs multiplexed with
Programmable GPIO signals
■ 3.3V Power Supply with 5V tolerant I/O
■ 0 to 70°C
* Third-party brands and names are the property of their respective
owners.
SMSC LAN9115
DATASHEET
Revision 1.1 (05-17-05)
1 page  
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.6 FIFO_INT—FIFO Level Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.7 RX_CFG—Receive Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.8 TX_CFG—Transmit Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3.9 HW_CFG—Hardware Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.10 RX_DP_CTRL—Receive Datapath Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.11 RX_FIFO_INF—Receive FIFO Information Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.12 TX_FIFO_INF—Transmit FIFO Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.13 PMT_CTRL— Power Management Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.14 GPIO_CFG—General Purpose IO Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 87
5.3.15 GPT_CFG-General Purpose Timer Configuration Register . . . . . . . . . . . . . . . . . . . . . . 88
5.3.16 GPT_CNT-General Purpose Timer Current Count Register . . . . . . . . . . . . . . . . . . . . . . 89
5.3.17 ENDIAN—Endian Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.18 FREE_RUN—Free-Run 25MHz Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3.19 RX_DROP– Receiver Dropped Frames Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register . . . . . . . . . . . . . . . . . 91
5.3.21 MAC_CSR_DATA – MAC CSR Synchronizer Data Register . . . . . . . . . . . . . . . . . . . . . 91
5.3.22 AFC_CFG – Automatic Flow Control Configuration Register . . . . . . . . . . . . . . . . . . . . . 92
5.3.23 E2P_CMD – EEPROM Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.24 E2P_DATA – EEPROM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.4 MAC Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.4.1 MAC_CR—MAC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.4.2 ADDRH—MAC Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.4.3 ADDRL—MAC Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.4.4 HASHH—Multicast Hash Table High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.4.5 HASHL—Multicast Hash Table Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.4.6 MII_ACC—MII Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.4.7 MII_DATA—MII Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.4.8 FLOW—Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.4.9 VLAN1—VLAN1 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.4.10 VLAN2—VLAN2 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.4.11 WUFF—Wake-up Frame Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.4.12 WUCSR—Wake-up Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.5 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.5.1 Basic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.5.2 Basic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.5.3 PHY Identifier 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.5.4 PHY Identifier 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.5.5 Auto-negotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.5.6 Auto-negotiation Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.5.7 Auto-negotiation Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.5.8 Mode Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.5.9 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.5.10 Special Control/Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.5.11 Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.5.13 PHY Special Control/Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.1 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.1.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 115
6.1.2 Special Restrictions on Back-to-Back Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.2 PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3 PIO Burst Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.4 RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.5 RX Data FIFO Direct PIO Burst Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SMSC LAN9115
5
DATASHEET
Revision 1.1 (05-17-05)
5 Page 
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
1.1 Internal Block Overview
This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal
Block Diagram".
+3.3V
25MHz
EEPROM
(Optional)
PME - Wakup Indicator Power Management
3.3V to 1.8V
Regulator
PLL
EEPROM
Controller
16-bit SRAM I/F
Host Bus Interface
(HBI)
PIO Controller
IRQ
FIFO_SEL
Interrupt
Controller
GP Timer
2kB to 14kB
Configurable TX FIFO
TX Status FIFO
RX Status FIFO
2kB to 14kB
Configurable RX FIFO
10/100
Ethernet
MAC
MIL - RX Elastic
Buffer - 128 bytes
MIL - TX Elastic
Buffer - 2K bytes
10/100
Ethernet
PHY
LAN
Optional
External PHY - MII
Interface
Figure 1.2 Internal Block Diagram
1.2
10/100 Ethernet PHY
The LAN9115 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY
can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in
either full or half duplex configurations. The PHY block includes auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
1.3 10/100 Ethernet MAC
The transmit and receive data paths are separate within the MAC allowing the highest performance
especially in full duplex mode. The data paths connect to the PIO interface Function via separate
busses to increase performance. Payload data as well as transmit and receive status is passed on
these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is
accessible from the host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a the MII (Media
Independent Interface) port internal to the LAN9115. The MAC CSR's also provides a mechanism for
accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
The Ethernet MAC can also communicate with an external PHY. This mode however, is optional.
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive
FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly
SMSC LAN9115
11
DATASHEET
Revision 1.1 (05-17-05)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN9115.PDF ] | |
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