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PDF IRCC2.0 Data sheet ( Hoja de datos )
| Número de pieza | IRCC2.0 | |
| Descripción | Infrared Communications Controller | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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IrCC 2.0
PRELIMINARY
Infrared Communications Controller
FEATURES
• Multi-Protocol Serial Communications
Controller
• Full IrDA v1.1 Implementation: 2.4 kbps -
115.2 kbps, 0.576 Mbps, 1.152 Mbps and 4
Mbps
• Consumer Infrared (Remote Control)
Interface
• SHARP Amplitude Shift Keyed Infrared
(ASK IR) Interface
• Direct Rx/Tx Infrared Diode Control (Raw)
and General Purpose Data Pins
• Programmable High-Speed Synchronous
Communications Engine (SCE) with a 128-
Byte FIFO and Programmable Threshold
• Programmable DMA Refresh Counter
• High-Speed NS16C550A-Compatible
Universal Asynchronous Receiver/
Transmitter Interface (ACE UART) with 16-
Byte Send and Receive FIFOs
• ISA Single-Byte and Burst-Mode DMA and
Interrupt-Driven Programmed I/O with Zero
Wait State and String Move Timing
• 16 Bit CRC-CCITT and 32 Bit IEEE 802
CRC32 Hardware CRC Generators
• Automatic Transceiver Control
• Transmit Pulse Width Limiter
• SCE Transmit Delay Timer
• IR Media Busy Indicator
GENERAL DESCRIPTION
This document describes the Infrared
Communications Controller (IrCC 2.0) function,
which is common to a number of SMSC
products. The IrCC 2.0 consists of two main
architectural blocks: the ACE 16C550A UART
and a Synchronous Communications Engine
(SCE) (Figure 2). It’s own unique register set
supports each block.
The IrCC 2.0 UART-driven IrDA SIR and SHARP
ASK modes are backward compatible
with current SMSC Super I/O and Ultra I/O
infrared implementations. The IrCC 2.0 SCE
supports IrDA v1.1 0.576 Mbps, 1.152 Mbps, 4
Mbps, and Consumer IR modes. All of the SCE-
driven modes can use DMA. The IrCC 2.0 offers
flexible signal routing and programmable output
control through the Raw mode interface, General
Purpose Data pins and Output Multiplexer. Chip-
level address decoding is required to access the
IrCC 2.0 register sets.
1 page  
NAME
Fast
GP Data
Table 4 - G. P. Port Signals
SIZE (BITS)
TYPE
DESCRIPTION
1
Output
General Purpose Data
1
Output
General Purpose Data
Fast
GP Data
The Fast pin always reflects the state of Fast, bit
6 of SCE Line Control Register A. The state of
Fast is independent of the IrCC 2.0 Block
Controls or the Output Multiplexer. The Fast pin
can be used at the chip level for IR Transceiver
configuration.
The G.P. Data pin typically reflects the state of
General Purpose Data, bit 5 of SCE Line Control
Register A. The state of G.P. Data is
independent of the IrCC 2.0 Block Controls or
the Output Multiplexer but will depend on the
ATC during transceiver programming cycles (see
the Automatic Transceiver Control section on
page 69).
NAME
D0-D7
A0-A2
nIOR
nIOW
AEN
DRQ
nDACK
TC
IRQ
IOCHRDY
nSRDY
SIZE (BITS)
8
3
1
1
1
1
1
1
1
1
1
Table 5 - HOST Signals
TYPE
DESCRIPTION
Bi-directional Host Data Bus
Input
IrCC 2.0 Register Address Bus
Input
ISA I/O Read
Input
ISA I/O Write
Input
ISA Address Enable
Output
DMA Request
Input
ISA DMA Acknowledge
Input
ISA DMA Terminal Count
Output
Interrupt Request
Output
ISA I/O Channel Ready
Output
ISA Synchronous Ready (Zero Wait State)
5
5 Page 
Table 9 - Representative Carrier Frequencies
CFD
001
005
009
013
017
021
025
029
033
037
041
045
049
053
057
061
Fc (kHz)
800.000
266.667
160.000
114.286
88.889
72.727
61.538
53.333
47.059
42.105
38.095
34.783
32.000
29.630
27.586
25.806
CFD
065
069
073
077
081
085
089
093
097
101
105
109
113
117
121
125
Fc (kHz)
24.242
22.857
21.622
20.513
19.512
18.605
17.778
17.021
16.327
15.686
15.094
14.545
14.035
13.559
13.115
12.698
CFD
129
133
137
141
145
149
153
157
161
165
169
173
177
181
185
189
Fc (kHz)
12.308
11.940
11.594
11.268
10.959
10.667
10.390
10.127
9.877
9.639
9.412
9.195
8.989
8.791
8.602
8.421
CFD
193
197
201
205
209
213
217
221
225
229
233
237
241
245
249
253
Fc (kHz)
8.247
8.081
7.921
7.767
7.619
7.477
7.339
7.207
7.080
6.957
6.838
6.723
6.612
6.504
6.400
6.299
Bit Rate Divider
Divider (BRD) and the Bit Rate (Fb) is as follows:
The Transmit and Receive Bit Rate Divider
register is used to extract a serial NRZ data
stream for the IrCC 2.0 SCE. The divider is eight
bits wide.
The input clock to the Bit Rate Divider is 100kHz
(Carrier Frequency Divider input clock ÷ 16).
The relationship between the Bit Rate
BRD = (.1MHz/Fb) - 1
For example, program the Bit Rate Divider with
55 ('37'Hex) for a .562ms Remote Control bit cell:
Fb = 1.786kHz. This is ~.5% accuracy. Table 10
contains representative BRD vs. Bit Rate
relationships. The Bit Rate range is 100kHz to
390.625Hz.
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IRCC2.0.PDF ] | |
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