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PDF HI5746 Data sheet ( Hoja de datos )
| Número de pieza | HI5746 | |
| Descripción | A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HI5746 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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®
Data Sheet
10-Bit, 40MSPS A/D Converter
The HI5746 is a monolithic, 10-bit, analog-to-digital
converter fabricated in a CMOS process. It is designed for
high speed applications where wide bandwidth and low
power consumption are essential. Its 40MSPS speed is
made possible by a fully differential pipelined architecture
with an internal sample and hold.
The HI5746 has excellent dynamic performance while
consuming only 225mW power at 40MSPS. Data output
latches are provided which present valid data to the output
bus with a latency of 7 clock cycles. It is pin-for-pin
functionally compatible with the HI5702 and the HI5703.
For internal voltage reference, please refer to the HI5767
data sheet.
Ordering Information
PART
NUMBER
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
HI5746KCB
0 to 70 28 Ld SOIC (W)
M28.3
HI5746KCBZ
www.DataSheet4U.com(Note)
HI5746KCBZ-T
(Note)
0 to 70
28 Ld SOIC (W)
(Pb-free)
28 Ld SOIC (W) Tape and Reel
(Pb-free)
M28.3
M28.3
HI5746KCA
0 to 70 28 Ld SSOP
M28.15
HI5746KCAZ
(Note)
0 to 70
28 Ld SSOP
(Pb-free)
M28.15
HI5746EVAL1
25 Evaluation Board
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
July 2004
HI5746
FN4129.5
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 40MSPS
• 8.8 Bits at fIN = 10MHz
• Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 225mW
• Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz
• On-Chip Sample and Hold
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V
• TTL/CMOS Compatible Digital Inputs
• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V
• Offset Binary or Two’s Complement Output Format
• Pb-free Available
Applications
• Professional Video Digitizing
• Medical Imaging
• Digital Communication Systems
• High Speed Data Acquisition
Pinout
HI5746
(SOIC, SSOP)
TOP VIEW
DVCC1 1
DGND1 2
DVCC1 3
DGND1 4
AVCC 5
AGND 6
VREF+ 7
VREF- 8
VIN+ 9
VIN- 10
VDC 11
AGND 12
AVCC 13
OE 14
28 D0
27 D1
26 D2
25 D3
24 D4
23 DVCC2
22 CLK
21 DGND2
20 D5
19 D6
18 D7
17 D8
16 D9
15 DFS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
HI5746
Electrical Specifications
CAVLC=C1=0pDFV; CTCA1==255.o0CV;;
DVCC2 = 3.0V, VREF+ =
Differential Analog Input;
2.5V; VREF - =
Typical Values
2.0V; fS
are Test
= 40 MSPS at 50%
Results at 25oC,
Duty
Cycle;
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input
Range (VIN+ - VIN-)
Maximum Peak-to-Peak Single-Ended
Analog Input Range
- ±0.5 -
- 1.0 -
V
V
Analog Input Resistance, RIN
Analog Input Capacitance, CIN
Analog Input Bias Current, IB+ or IB-
Differential Analog Input Bias Current
IBDIFF = (IB+ - IB-)
Full Power Input Bandwidth, FPBW
(Note 3)
(Note 3)
(Note 3)
- 1 - MΩ
- 10 - pF
-10 - +10 µA
- ±0.5 -
µA
- 250 - MHz
Analog Input Common Mode Voltage Range
(VIN+ + VIN-)/2
REFERENCE INPUT
Differential Mode (Note 2)
0.25 - 4.75 V
Total Reference Resistance, RL
Positive Reference Current, IREF+
Negative Reference Current, IREF -
Positive Reference Voltage Input, VREF+
Negative Reference Voltage Input, VREF-
Reference Common Mode Voltage
(VREF+ + VREF-)/2
DC BIAS VOLTAGE
VREF+ to AGND
(Note 2)
(Note 2)
(Note 2)
- 2.5K -
- 1.07 -
- 21 -
- 2.5 -
- 2.0 -
- 2.25 -
Ω
mA
µA
V
V
V
DC Bias Voltage Output, VDC
Maximum Output Current
- 3.2 -
V
- - 0.4 mA
DIGITAL INPUTS
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Input Logic High Current, IIH
Input Logic Low Current, IIL
Input Capacitance, CIN
DIGITAL OUTPUTS
CLK, DFS, OE
CLK, DFS, OE
CLK, DFS, OE, VIH = 5V
CLK, DFS, OE, VIL = 0V
2.0 - - V
- - 0.8 V
-10.0
-
+10.0
µA
-10.0
-
+10.0
µA
- 7 - pF
Output Logic High Voltage, VOH
Output Logic Low Voltage, VOL
Output Three-State Leakage Current, IOZ
Output Logic High Voltage, VOH
Output Logic Low Voltage, VOL
IOH = 100µA; DVCC2 = 5V
IOL = 100µA; DVCC2 = 5V
VO = 0/5V; DVCC2 = 5V
IOH = 100µA; DVCC2 = 3V
IOL = 100µA; DVCC2 = 3V
4.0 - - V
- - 0.5 V
- ±1 ±10 µA
2.4 - - V
- - 0.5 V
5
5 Page 
Typical Performance Curves (Continued)
3.30
HI5746
9.0
3.20
8.8
3.10
3.00
-40
-20
0 20 40
TEMPERATURE (oC)
60
80
FIGURE 21. DC BIAS VOLTAGE (VDC) vs TEMPERATURE
8.6
8.4
8.2
-40
-20
0
20 40 60 80
TEMPERATURE (oC)
FIGURE 22. EFFECTIVE NUMBER OF BITS F(ENOB) vs
TEMPERATURE
FIGURE 23. 2048 POINT FFT PLOT
Detailed Description
Theory of Operation
The HI5746 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 25 depicts
the circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
sampling clock which is a non-overlapping two phase signal, φ1
and φ2, derived from the master sampling clock. During the
sampling phase, φ1, the input signal is applied to the sampling
capacitors, CS. At the same time the holding capacitors, CH,
are discharged to analog ground. At the falling edge of φ1 the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase, φ2, the two bottom plates of
the sampling capacitors are connected together and the
holding capacitors are switched to the op amp output nodes.
The charge then redistributes between CS and CH completing
one sample-and-hold cycle. The front end sample-and-hold
11
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
fIN = 10MHz
fS = 40 MSPS
512
FREQUENCY BIN
1023
FIGURE 24. 2048 POINT FFT SPECTRAL PLOT
output is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fully-
differential output for the converter core. During the sampling
phase, the VIN pins see only the on-resistance of a switch and
CS. The relatively small values of these components result in a
typical full power input bandwidth of 250MHz for the converter.
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HI5746.PDF ] | |
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