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PDF HI5728 Data sheet ( Hoja de datos )
| Número de pieza | HI5728 | |
| Descripción | A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
HI5728
July 1999 File Number 4321.4
10-Bit, 125/60MSPS, Dual High Speed
CMOS D/A Converter
The HI5728 is a 10-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. Operating from a
single +5V or +3V supply, the converter provides 20.48mA of
full scale output current and includes an input data register.
Low glitch energy and excellent frequency domain
performance are achieved using a segmented architecture.
A 60MSPS version and an 8-bit (HI5628) version are also
available. Comparable single DAC solutions are the HI5760
(10-bit) and the HI5660 (8-bit). This DAC is a member of the
CommLink™ family of communication devices.
Ordering Information
PART
NUMBER
HI5728IN
HI5728/6IN
www.DataSheet4U.comHI5728EVAL1
TEMP.
RANGE
(oC) PACKAGE
PKG. NO.
MAX
CLOCK
SPEED
-40 to 85 48 Ld LQFP Q48.7x7A 125MHz
-40 to 85 48 Ld LQFP Q48.7x7A 60MHz
25 Evaluation Platform
125MHz
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .125MSPS
• Low Power . . . . . . . . . . . . . . . 330mW at 5V, 54mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . ±1 LSB
• Differential Linearity . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB
• Gain Matching (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .0.5%
• SFDR at 5MHz Output . . . . . . . . . . . . . . . . . . . . . . .68dBc
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
• Internal Voltage Reference
• Dual 10-Bit D/A Converters on a Monolithic Chip
Applications
• Wireless Local Loop
• Direct Digital Frequency Synthesis
• Wireless Communications
• Signal Reconstruction
• Arbitrary Waveform Generators
• Test Equipment/Instrumentation
• High Resolution Imaging Systems
Pinout
HI5728
(LQFP)
TOP VIEW
ID6
ID5
ID4
ID3
ID2
ID1
ID0 (LSB)
SLEEP
DVDD
DGND
NC
AVDD
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
1213 14 15 16
25
17 18 19 20 21 22 23 24
QD6
QD5
QD4
QD3
QD2
QD1
QD0 (LSB)
DVDD
DGND
NC
AVDD
AGND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CommLink™ is a trademark of Intersil Corporation.
1 page  
HI5728
Absolute Maximum Ratings
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . . DVDD +0.3V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . ±50µA
Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AVDD +0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA(oC/W)
TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Power Dissipation
TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .930mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given is
per channel except for ‘Power Supply Characteristics.’
PARAMETER
TEST CONDITIONS
HI5728IN
TA = -40oC TO 85oC
MIN TYP MAX
UNITS
SYSTEM PERFORMANCE (Per Channel)
Resolution
10 -
- Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 7)
-1 ±0.5 +1
LSB
Differential Linearity Error, DNL
(Note 7)
-0.5 ±0.25 +0.5 LSB
Offset Error, IOS
Offset Drift Coefficient
(Note 7)
(Note 7)
-0.025
+0.025 % FSR
- 0.1 - ppm
FSR/oC
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
-10 ±2 +10 % FSR
-10 ±1 +10 % FSR
Full Scale Gain Drift
With External Reference (Note 7)
- ±50 -
ppm
FSR/oC
With Internal Reference (Note 7)
- ±100 -
ppm
FSR/oC
Gain Matching Between Channels
-0.5 0.1 0.5
dB
I/Q Channel Isolation
Output Voltage Compliance Range
FOUT = 10MHz
(Note 3)
- 80 -
-0.3 - 1.25
dB
V
Full Scale Output Current, IFS
DYNAMIC CHARACTERISTICS (Per Channel)
2 - 20 mA
Maximum Clock Rate, fCLK
Output Settling Time, (tSETT)
(Note 3)
0.1% (±1 LSB, equivalent to 9 Bits) (Note 7)
0.05% (±1/2 LSB, equivalent to 10 Bits) (Note 7)
125 -
- MHz
- 20 -
ns
- 35 -
ns
Singlet Glitch Area (Peak Glitch)
Output Rise Time
RL = 25Ω (Note 7)
Full Scale Step
- 35 - pV•s
- 1.5 -
ns
Output Fall Time
Full Scale Step
- 1.5 -
ns
Output Capacitance
- 10 -
pF
Output Noise
IOUTFS = 20mA
- 50 - pA/√Hz
IOUTFS = 2mA
- 30 - pA/√Hz
5
5 Page 
HI5728
Typical Performance Curves, 5 Volt Power Supply (Continued)
320
310
300
290
280
270
260
250
240
230
220
210
0
20 40 60 80 100 120
CLOCK RATE (MSPS)
FIGURE 19. POWER vs CLOCK RATE, fCLK/fOUT = 10, IOUT = 20mA
Typical Performance Curves, 3V Power Supply
80
75 -6dBFS
70
0dBFS
65
60
-12dBFS
55
50
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
OUTPUT FREQUENCY (MHz)
FIGURE 20. SFDR vs fOUT, CLOCK = 5MSPS
80
0dBFS
75
-6dBFS
70
-12dBFS
65
60
1 2 3 4 5 6 7 8 9 10
OUTPUT FREQUENCY (MHz)
FIGURE 21. SFDR vs fOUT, CLOCK = 25MSPS
80
75
-6dBFS
70
-12dBFS
65
60
0dBFS
55
50
0 2 4 6 8 10 12 14 16 18 20
OUTPUT FREQUENCY (MHz)
FIGURE 22. SFDR vs fOUT, CLOCK = 50MSPS
80
0dBFS
75
70 -6dBFS
65
-12dBFS
60
55
50
45
0 5 10 15 20 25 30 35 40 45
OUTPUT FREQUENCY (MHz)
FIGURE 23. SFDR vs fOUT, CLOCK = 100MSPS
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HI5728.PDF ] | |
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