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PDF HI5721 Data sheet ( Hoja de datos )
| Número de pieza | HI5721 | |
| Descripción | A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
HI5721
June 1999 File Number 3949.7
10-Bit, 125 MSPS, High Speed D/A
Converter
The HI5721 is a 10-bit, 125 MSPS, high speed D/A
converter. The converter incorporates a 10-bit, input data
register with quadrature data logic capability and current
outputs. The HI5721 features low glitch energy and excellent
frequency domain specifications.
Ordering Information
PART
NUMBER
HI5721BIP
HI5721BIB
HI5721-EVP
HI5721-EVS
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
-40 to 85 28 Ld PDIP
E28.6
-40 to 85 28 Ld SOIC (W)
M28.3
25 Evaluation Board (PDIP)
25 Evaluation Board (SOIC)
www.DataSheet4U.com
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 125 MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .700mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . 1.5 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pV•s
• TTL/CMOS Compatible Inputs
• Improved Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . 0.5ns
• Excellent Spurious Free Dynamic Range
• Improved Second Source for the AD9721
Applications
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• HDTV
• Test Equipment
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout
HI5721
(PDIP, SOIC)
TOP VIEW
D9 (MSB) 1
D8 2
D7 3
D6 4
D5 5
D4 6
D3 7
D2 8
D1 9
D0 (LSB) 10
CLOCK 11
NC 12
INVERT 13
VCC 14
28 DGND
27 DVEE
26 CTRL AMP IN
25 REF OUT
24 CTRL AMP OUT
23 REF IN
22 AVEE
21 IOUT
20 IOUT
19 ARTN
18 AGND
17 RSET
16 DVEE
15 DGND
3-34
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1 page  
HI5721
Electrical Specifications ATAVE=E2,5DoVCEfEor=A-l4l .T9y4pitcoa-l5V.a4l6uVe,sVC(CCo=n+ti4n.u7e5dto) +5.25V, CTRL AMP IN = REF OUT,
PARAMETER
TEST CONDITIONS
HI5721BI
TA = -40oC TO 85oC
MIN TYP MAX
UNITS
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, REF OUT
Internal Reference Voltage Drift
(Note 4)
(Note 3)
-1.15
-
-1.25
100
-1.35
-
V
µV/oC
Internal Reference Output Current Sink/Source
Capability
(Note 3)
-50 - +500 µA
Amplifier Input Impedance
(Note 3)
- 10 - MΩ
Amplifier Large Signal Bandwidth
4.0VP-P Sine Wave Input, to Slew Rate Limited
-
1
- MHz
(Note 3)
Amplifier Small Signal Bandwidth
Reference Input Impedance
1.0VP-P Sine Wave Input, to -3dB Loss (Note 3)
-
10
-
MHz
(Note 3)
- 4.6 -
kΩ
Reference Input Multiplying Bandwidth
DIGITAL INPUTS (D9-D0, CLK, INVERT)
RL = 50Ω, 100mV Sine Wave, to -3dB Loss at - 75 - MHz
IOUT (Note 3)
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Input Logic Current, IIH
Input Logic Current, IIL
Digital Input Capacitance, CIN
TIMING CHARACTERISTICS
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 3)
2.0 -
-
- - 0.8
- - 400
- - 700
- 3.0 -
V
V
µA
µA
pF
Data Setup Time, tSU
Data Hold Time, tHLD
Propagation Delay Time, tPD
CLK Pulse Width, tPW1, tPW2
POWER SUPPLY CHARACTERISITICS
See Figure 3 (Note 3)
See Figure 3 (Note 3)
See Figure 3 (Note 3)
See Figure 3 (Note 3)
2.0 -
0.5 -
- 4.5
1.0 0.85
-
-
-
-
ns
ns
ns
ns
IDVEE
IAVEE
VCC
Power Dissipation
(Note 4)
(Note 4)
(Note 4)
(Note 4)
- 100 110 mA
- - 15 mA
- 14 25 mA
-
700 775
mW
Power Supply Rejection Ratio
VCC ±5%, VEE ±5%
- 50 - µA/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 640µA). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. All devices are 100% tested at 25oC. 100% productions tested at temperature extremes for military temperature devices, sample tested for in-
dustrial temperature devices.
5. Spectral measurements made without external filtering.
3-38
5 Page 
HI5721
-0.6 TO -1.2V
1MHz (MAX)
RSET
RT
18Ω
HI5721
20
RSET
19
CTRL AMP IN
18
CTRL AMP
OUT
17
REF IN
FIGURE 19. LOW FREQUENCY MULTIPLYING CIRCUIT
If higher multiplying frequencies are desired, the reference
input can be directly driven. The analog signal range is -3.3V
to -4.25V. The multiplying signal must be capacitively
coupled into REF IN onto a DC bias between -3.3V to -4.25V
(-3.8V typically).
HI5721
2nF 383Ω
50Ω 120Ω
17
REF IN
≅ -3.8V
AVEE
FIGURE 20. WIDEBAND MULTIPLYING CIRCUIT
Outputs
The outputs IOUT and IOUT are complementary current
outputs. Current is steered to either IOUT or IOUT in
proportion to the digital input code. The sum of the two
currents is always equal to the full scale current minus one
LSB. The current output can be converted to a voltage by
using a load resistor. Both current outputs should have the
same load resistor (64Ω typically). By using a 64Ω load on
the output, a 50Ω effective output resistance (ROUT) is
achieved due to the 227Ω (±15%) parallel resistance seen
looking back into the output. This is the nominal value of the
R2R ladder of the DAC. The 50Ω output is needed for
matching the output with a 50Ω line. The load resistor should
be chosen so that the effective output resistance (ROUT)
matches the line resistance. The output voltage is:
VOUT = IOUT x ROUT.
IOUT is defined in the reference section. The compliance
range of the output is from -1.5V to 3V, with a 1VP-P voltage
swing allowed within this range. However, if it is desired that
the output be offset above zero volts, it is necessary that pin
19 (ARTN) be connected to the same voltage as the load
resistor, not to exceed 3V.
Glitch
TABLE 1. INPUT CODING vs CURRENT OUTPUT
INPUT CODE (D9-D0)
11 1111 1111
IOUT (mA)
-20.48
IOUT (mA)
0
10 0000 0000
-10.24
-10.24
00 0000 0000
0 -20.48
The output glitch of the HI5721 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
to change before another. To minimize this the Intersil
HI5721 employes an internal register, just prior to the current
sources, that is updated on the clock edge. Lastly the worst
case glitch usually happens at the major transition i.e.,
01 1111 1111 to 10 0000 0000. But in the HI5721 the glitch
is moved to the 00 0001 1111 to 11 1110 0000 transition.
This is achieved by the split R/2R segmented current source
architecture. This decreases the amount of current switching
at any one time and makes the glitch practically constant
over the entire output range. By making the glitch a constant
size over the entire output range this effectively integrates
this error out of the end application.
In measuring the output glitch of the HI5721 the output is
terminated into a 64Ω load. The glitch is measured at the
major carrys throughout the DAC’s output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 21 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt • seconds (pV • s).
HI5721
(20) IOUT
125MHz SCOPE
LOW PASS
FILTER
64Ω 50Ω
FIGURE 21. GLITCH TEST CIRCUIT
3-44
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HI5721.PDF ] | |
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