PDF HI3026 Data sheet ( Hoja de datos )

Número de pieza	HI3026
Descripción	Flash A/D Converter
Fabricantes	Intersil Corporation
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No Preview Available ! HI3026 August 1997 8-Bit, 120 MSPS, Flash A/D Converter Features • Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB • Integral Linearity Error . . . . . . . . . . . . . . . . . . ±0.5 LSB • Integral Linearity Compensation Circuit • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . 21pF • Wide Analog Input Bandwidth . . . . . . . . . . . . . 150MHz • Low Power Consumption . . . . . . . . . . . . . . . . . .760mW • Internal 1/2 Frequency Divider Circuit (w/Reset Function) • CLK/2 Clock Output • Compatible with ECL, PECL and TTL Digital Input Levels • 1:2 Demultiplexed Output Pin • Surface Mounting Package • Direct Replacement for Sony CXA3026Q Applications • RGB Graphics Processing (LCD, PDP) • Digital Oscilloscopes • Digital Communications (QPSK, QAM) www.DataSheet4U.com • Magnetic Recording (PRML) Description The HI3026 is an 8-bit, high-speed, ﬂash analog-to-digital converter optimized for high speed, low power, and ease of use. With a 120 MSPS encode rate capability and full-power analog bandwidth of 150MHz, this component is ideal for appli- cations requiring the highest possible dynamic performance. To minimize system cost and power dissipation, only a +5V power supply is required. The HI3026’s clock input interfaces directly to TTL, ECL, or PECL logic and will operate with single- ended inputs. The user may select 16-bit demultiplexed output or 8-bit single channel digital outputs. The demultiplexed mode interleaves the data through two 8-bit channels at 1/2 the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces, while allowing the A/D con- verter to be clocked to the full 120 MSPS conversion rate. Fabricated with an advanced Bipolar process, the HI3026 is provided in a space-saving 48-lead MQFP surface mount plastic package and is speciﬁed over the -20oC to 75oC tem- perature range. For a faster clock rate, please refer to the HI3026A (140 MSPS), AnswerFAX Document number 4246. Ordering Information PART NUMBER HI3026JCQ HI3026EVAL TEMP. RANGE (oC) PACKAGE PKG. NO. -20 to 75 48 Ld MQFP Q48.12x12-S 25 Evaluation Board Pinout HI3026 (MQFP) TOP VIEW DVEE3 VRB AGND VRM1 AVCC VIN VRM2 AVCC VRM3 AGND VRT DGND3 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 1213 14 15 16 17 18 19 20 21 22 25 23 24 P1D3 P1D2 P1D1 P1D0 DGND2 DVCC2 DVCC1 DGND1 P2D7 P2D6 P2D5 P2D4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 \| Copyright © Intersil Corporation 1999 4-1362 File Number 4109.3 1 page HI3026 Electrical Speciﬁcations DTAVC=C215,o2C, AVCC, DGND3 (Continued) = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, PARAMETER TEST CONDITIONS Error Rate (Note 7) fC = 120 MSPS, fIN = 1kHz Full Scale, DMUX Mode, Error > 16 LSB fC = 120 MSPS, fIN = 29.999MHz Full Scale, DMUX Mode, Error > 16 LSB fC = 100 MSPS, fIN = 24.999MHz Full Scale, Straight Mode, Error > 16 LSB POWER SUPPLY Supply Current, ICC Supply Current, IEE Power Consumption (Note 8), PD NOTES: 4. RREF: Resistance value between VRT and VRB. 5. IREF = V-----R--R--T---R--–--E--V--F--R-----B- . 6. T = f--1C--- . 7. The unit of measure TPS: Times Per Sample. 8. PD = (ICC + IEE) • VCC + (---V----R----T-----–-----V----R----B----)--2-- VREF . MIN - - - 125 0.4 660 TYP - - - MAX 10-12 10-9 10-9 145 185 0.6 0.8 760 960 UNITS TPS TPS TPS mA mA mW Timing Diagrams VIN CLK P1D0 TO D7 P2D0 TO D7 CLK OUT N-1 tDS t N+2 N+3 N N+1 tPW1 tPW0 tDCLK 2V 0.8V tD02 N-2 N-3 tD01 t + 1ns 2V 0.8V 2V 0.8V N 2V 0.8V N-1 N+2 N-1 RESET PULSE tPWR FIGURE 1. DEMUX MODE TIMING CHART (SELECT = VCC) 4-1366 5 Page HI3026 The A/D converter can operate at fC (Min) = 100 MSPS in this mode. Digital Input Level and Supply Voltage Settings The logic input level for the HI3026 supports ECL, PECL and TTL levels. The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level. TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS DIGITAL INPUT LEVEL ECL PECL TTL DVEE3 -5V DGND3 0V SUPPLY VOLTAGE 5V 0V +5V +5V 0V +5V +5V APPLICATION CIRCUITS Figures 18, 21 Figures 19, 22 Figures 20, 23 CLK HI3026 CLK A RESETN CLK 8 BITS CLKOUT DATA HI3026 CLK B RESETN 8 BITS CLKOUT DATA FIGURE 9. WHEN THE RESET PULSE IS NOT USED CLK HI3026 CLK A RESETN 8 BITS CLK RESET PULSE CLKOUT DATA RESET PULSE HI3026 CLK B RESETN 8 BITS CLKOUT DATA FIGURE 10. WHEN THE RESET PULSE IS USED Typical Performance Curves 170 160 150 140 130 -25 25 AMBIENT TEMPERATURE (oC) FIGURE 11. CURRENT CONSUMPTION vs AMBIENT TEMPERATURE CHARACTERISTICS 170 160 150 140 fIN = fCLK 4 -1kHz 130 DMUX MODE CL = 5pF 75 0 60 120 CONVERSION RATE (MSPS) FIGURE 12. CURRENT CONSUMPTION vs CONVERSION RATE CHARACTERISTICS RESPONSE 4-1372 11 Page

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