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PDF HI1172 Data sheet ( Hoja de datos )
| Número de pieza | HI1172 | |
| Descripción | Video A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HI1172 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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HI1172
August 1997
6-Bit, 20 MSPS,
Video A/D Converter (CMOS)
Features
Description
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-Bit
• Maximum Sampling Frequency . . . . . . . . . . . 20 MSPS
• Low Power Consumption at 20 MSPS (Typ)
(Reference Current Excluded) . . . . . . . . . . . . . . .40mW
• Built-In Sample and Hold Circuit
• Three-State TTL Compatible Output
• Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Single
• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 4pF
• Reference Impedance . . . . . . . . . . . . . . . . . . 250Ω (Typ)
Applications
HI1172 is a 6-bit, CMOS A/D converter for video use. The
adoption of a 2-step parallel conversion achieves speeds of
20 MSPS minimum, 35 MSPS typical.
Ordering Information
PART
NUMBER
HI1172JCP
HI1172JCB
TEMP.
RANGE (oC)
PACKAGE
-20 to 75 16 Ld PDIP
-20 to 75 16 Ld SOIC
PKG. NO.
E16.3A-S
M16.2-S
• Video Digitizing
• Wireless Communications
Pinout
www.DataSheet4U.com
HI1172
(PDIP, SOIC)
TOP VIEW
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
CLK 7
DVSS 8
16 AVSS
15 DVDD
14 AVDD
13 VRB
12 VIN
11 VRT
10 AVDD
9 DVDD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
4-1062
File Number 4102.1
1 page  
Test Circuits
HI1172
+V
S2
- S1 : ON IF A < B
+ S1 S2 : ON IF B > A
-V
A<B A>B
VIN DUT
HI1172
COMPARATOR
6
A6 B6
6
DVM
A1
A0
“0”
B1
B0
“1”
CLK (20MHz)
CONTROLLER
BUFFER
000 • • • 00
6 TO
111 • • • 10
FIGURE 1. INTEGRAL NON-LINEARITY ERROR, DIFFERENTIAL NON-LINEARITY, OFFSET VOLTAGE
I
2V
fC -1kHz
SG
1V
1
AMP
2
NTSC
SIGNAL
40 IRE
SOURCE 100 MODULATION
2V
IAE
0
-40
BURST
SYNC
1V
SG
(CW)
fC
VIN
HI1172
6 TTL
ECL
TTL
ECL
HI20201
1
6 10-BIT
D/A 2
CLK
620
-5.2V
620
-5.2V
ERROR RATE
HPF
COUNTER
VECTOR
SCOPE
DG
DP
FIGURE 2. MAXIMUM OPERATIONAL SPEED, DIFFERENTIAL GAIN ERROR, DIFFERENTIAL PHASE ERROR
I
2.0V
1.0V
VDD
VRT
VIN
VRB
CLK
GND
IOL
VOL +
-
2.0V
1.0V
VDD
VRT
VIN
VRB
CLK
GND
IOH
VOH
+
-
FIGURE 3. DIGITAL OUTPUT CURRENT TEST CIRCUIT
4-1066
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HI1172.PDF ] | |
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