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PDF WF2M32-XXX5 Data sheet ( Hoja de datos )
| Número de pieza | WF2M32-XXX5 | |
| Descripción | 2Mx32 5V Flash Module | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
WF2M32-XXX5
2Mx32 5V Flash Module
FEATURES
Access Time of 90, 120, 150ns
Packaging:
• 66 pin, PGA Type, 1.185" square, Hermetic
Ceramic HIP (Package 401).
• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880")
square (Package 510) 3.56mm (0.140") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (FIGURE 3)
Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8
chip
• Any combination of sectors can be erased. Also
supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 2Mx32
Commercial, Industrial, and Military
Temperature Ranges
5 Volt Read and Write. 5V ± 10% Supply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector
not being erased.
RESET# pin resets internal state machine to the
read mode.
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation, Separate Power and
Ground Planes to improve noise immunity
* This product is subject to change without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
www.DataSheet4U.com
FIGURE 1 – PIN CONFIGURATION FOR WF2M32-XHX5
Top View
1 12 23
I/O8 WE2# I/O15
34 45 56
I/O24
VCC I/O31
I/O9
CS2#
I/O14
I/O25
CS4#
I/O30
I/O10 GND I/O13
I/O26 WE4#
I/O29
A14 I/O11 I/O12
A7 I/O27
I/O28
A16 A10 OE#
A12 A4
A1
A11 A9
A17
A20 A5
A2
A0 A15 WE1#
A13 A6
A3
A18 VCC I/O7
A8 WE3#
I/O23
I/O0
CS1#
I/O6
I/O16
CS3#
I/O22
I/O1 A19
I/O5
I/O17 GND I/O21
I/O2 I/O3 I/O4
11 22
33
I/O18
I/O19
I/O20
44 55 66
Pin Description
I/O0-31 Data Inputs/Outputs
A0-20 Address Inputs
WE1-4# Write Enables
CS1-4# Chip Selects
OE# Output Enable
VCC Power Supply
GND Ground
OE#
A0-20
Block Diagram
WE1# CS1#
WE2# CS2#
WE3# CS3#
2M x 8
2M x 8
2M x 8
WE4# CS4#
2M x 8
8
I/O0-7
8
I/O8-15
8
I/O16-23
8
I/O24-31
RESET# internally tied to VCC in the HIP package for this pin con-
figuration. See Alternate Pin Configuration with RESET# tied to pin
12 for system control of reset (FIGURE 10, page 11).
October 2004
Rev. 5
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
WF2M32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Write Cycle Time
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
Symbol
tAVAV
tWLEL
tELEH
tAVEL
tDVEH
tEHDX
tELAX
tEHEL
tWHWH1
tWHWH2
tGHEL
tWC
tWS
tCP
tAS
tDS
tDH
tAH
tCPH
tOEH
-90
Min Max
90
0
45
0
45
0
45
20
300
15
0
44
256
10
-120
Min Max
120
0
50
0
50
0
50
20
300
15
0
44
256
10
-150
Min Max
150
0
50
0
50
0
50
20
300
15
0
44
256
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
sec
sec
ns
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
FIGURE 3 – AC TEST CIRCUIT
Current Source
D.U.T.
Ceff = 50 pf
Current Source
IOL
IOH
VZ ≈ 1.5V
(Bipolar Supply)
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
VIL = 0, VIH = 3.0
5
1.5
1.5
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ý.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Unit
V
ns
V
V
FIGURE 4 – RESET TIMING DIAGRAM
RESET#
tRP
tReady
October 2004
Rev. 5
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
WF2M32-XXX5
FIGURE 10 – ALTERNATE PIN CONFIGURATION FOR WF2M32I-XHX5
TOP VIEW
1 12 23
34 45 56
I/O8 RESET# I/O15
I/O24
VCC I/O31
I/O9
CS2#
I/O14
I/O25
CS4#
I/O30
I/O10 GND
I/O13
I/O26
NC I/O29
A14
I/O11
I/O12
A7 I/O27
I/O28
A16 A10
OE#
A12 A4
A1
A11 A9
A17
NC A5
A2
A0 A15 WE#
A13 A6
A3
A18 VCC I/O7
A8 A20 I/O23
I/O0
CS1#
I/O6
I/O16
CS3#
I/O22
I/O1 A19
I/O5
I/O17 GND I/O21
I/O2 I/O3
I/O4
11 22
33
I/O18
I/O19
I/O20
44 55 66
PIN DESCRIPTION
I/O0-31
A0-20
WE#
Data Inputs/Outputs
Address Inputs
Write Enable
CS1-4#
OE#
Chip Selects
Output Enable
VCC Power Supply
GND Ground
RESET#
Reset
RESET#
WE#
OE#
A0-20
BLOCK DIAGRAM
CS1#
CS2#
CS3#
2M x 8
2M x 8
2M x 8
CS4#
2M x 8
8
I/O0-7
8
I/O8-15
8
I/O16-23
8
I/O24-31
FIGURE 11 – ALTERNATE PIN CONFIGURATION FOR WF2M32U-XG2UX5
TOP VIEW
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
10 60
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
PIN DESCRIPTION
0.940"
The WEDC 68 lead G2U CQFP fills the
same fit and function as the JEDEC 68 lead
CQFJ or 68 PLCC. But the G2U has the
TCE and lead inspection advantage of the
CQFP form.
I/O0-31
A0-20
WE#
CS#
OE#
VCC
GND
RESET#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Reset
BLOCK DIAGRAM
RESET#
CS#
WE#
OE#
A0-20
2M x 8
2M x 8
2M x 8
2M x 8
October 2004
Rev. 5
8
I/O0-7
8
I/O8-15
8
I/O16-23
8
I/O24-31
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet WF2M32-XXX5.PDF ] | |
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