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PDF EM6AA320 Data sheet ( Hoja de datos )
| Número de pieza | EM6AA320 | |
| Descripción | 8M x 32 DDR SDRAM | |
| Fabricantes | Etron Technology | |
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EtronTech
Revision History
EM6AA320
Revision 0.6(May, 2006) Preliminary Spec
Delete confidential wording.
Revision 0.5(May, 2003) Preliminary Spec
Revised the AC Timing of tCLK at CL=4 for pure VDD/VDDQ=2.8V spec.
Revision 0.4(May, 2003) Preliminary Spec
Revised the AC Timing of tCLK at CL=4 for pure VDD/VDDQ=2.5V spec.
Revision 0.3(March, 2003) Preliminary Spec
Separated pure VDD/VDDQ=2.8V spec for graphics application.
Revision 0.2(March, 2003) Preliminary Spec
Separated pure VDD/VDDQ=2.5V spec for mobile PC graphics application.
Initially defined VDD=VDDQ=2.5V 275MHz(-3.6ns) preliminary specification.
Combined VDD=VDDQ=2.5V 200MHz(-5ns) and 250MHz(-4ns) specification from rev. 0.1 for both
2.8V and 2.5V.
Revision 0.1(February, 2003) Preliminary Spec
Defined EM6AA320BI-3.6(275MHz).
Added special code “M” in EM6AA320BI-4M for indicating 2.5V power supply.
Added special code “M” in EM6AA320BI-5M for indicating 2.5V power supply.
Removed EM6AA320BI-3.5(285MHz).
Revised the DC current of IDD2P, IDD2N, IDD3P, IDD3N, IDD4R and IDD4W for all speed grade.
Revision 0.0(July, 2002) Preliminary Spec
Initially defined target specification.
1 page  
EtronTech
8Mx32 DDR SDRAM
EM6AA320
Pin Descriptions
Table 1. Pin Details of EM6AA320
Symbol
CK, CK#
CKE
BA0, BA1
A0-A11
CS#
RAS#
CAS#
WE#
DQS0-DQS3
DM0 - DM3
DQ0 - DQ31
VDD
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input /
Output
Input
Input /
Output
Supply
Description
Differential Clock: CK, CK# are driven by the system clock. All SDRAM input
commands are sampled on the positive edge of CK. Both CK and CK# increment the
internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next
clock cycle and the state of output and burst address is frozen as long as the CKE
remains low. When all banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes.
Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. They also define which Mode Register or
Extended Mode Register is loaded during a Mode Register Set command.
Address Inputs: A0-A11 are sampled during the Bank Activate command (row
address A0-A11) and Read/Write command (column address A0-A7, and A9 with A8
defining Auto Precharge) to select one location out of the memory array in the
respective bank. During a Precharge command, A8 is sampled to determine if all
banks are to be precharged (A8 = HIGH). The address inputs also provide the op-
code during a Mode Register Set or Extended Mode Register Set command.
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH" either
the BankActivate command or the Precharge command is selected by the WE#
signal. When the WE# is asserted "HIGH," the BankActivate command is selected
and the bank designated by BS is turned on to the active state. When the WE# is
asserted "LOW," the Precharge command is selected and the bank designated by BS
is switched to the idle state after the precharge operation.
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CK. When RAS# is held "HIGH" and CS# is asserted "LOW" the column access is
started by asserting CAS# "LOW" Then, the Read or Write command is selected by
asserting WE# "HIGH " or “LOW".
Write Enable: The WE# signal defines the operation commands in conjunction with
the RAS# and CAS# signals and is latched at the positive edges of CK. The WE#
input is used to select the BankActivate or Precharge command and Read or Write
command.
Bidirectional Data Strobe: The DQSx signals are mapped to the following data
bytes: DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, DQS3 to
DQ24-DQ31.
Data Input Mask: DM0-DM3 are byte specific. Input data is masked when DM is
sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23-
DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0.
Data I/O: The DQ0-DQ31 input and output data are synchronized with the positive
edges of CK and CK#. The I/Os are byte-maskable during Writes.
Power Supply: Power for the input buffers and core logic.
5
Rev 0.6
May 2006
5 Page 
EtronTech
8Mx32 DDR SDRAM
EM6AA320
Decoupling Capacitance Guide Line
Symbol
Parameter
CDC1 Decouping Capacitance between VDD and VSS
CDC2 Decouping Capacitance between VDDQ and VSSQ
Value
0.1+0.01
0.1+0.01
Unit
uF
uF
AC Input Operating Conditions
(VDD = 2.8V ± 5%, TA = 0~70 °C)
Symbol
Parameter
VIH Input High Voltage; DQ
VIL Input Low Voltage; DQ
VID Clock Input Differential Voltage; Ck & CK#
VIX Clock Input Crossing Point Voltage; Ck & CK#
Min
VREF+0.4
-
0.8
0.5xVDDQ-0.2
Max
-
VREF-0.4
VDDQ+0.6
0.5xVDDQ+0.2
Unit
V
V
V
V
Note
AC Operating Test Conditions
(VDD = 2.8V ± 5%, TA = 0~70 °C)
Reference Level of Output Signals (VRFE)
CK & CK# signal maximum peak swing
Output Load
Input Signal Levels
Input Signals Slew Rate
Input timing measurement reference level
Output timing measurement reference level
Reference Level of Input Signals
0.5 x VDDQ
1.5V
See Figure. A Test Load
VREF+0.4 V / VREF-0.4 V
1 V/ns
VREF
VTT
0.5 x VDDQ
Figure A. Test Load
VTT=0.5 x VDDQ
DQ,DQS
Z0=50 W
50Ω
30pF VREF=0.5 x VDDQ
11
Rev 0.6
May 2006
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet EM6AA320.PDF ] | |
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