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PDF EM6605 Data sheet ( Hoja de datos )
| Número de pieza | EM6605 | |
| Descripción | 4 bit Microcontroller | |
| Fabricantes | EM Microelectronic | |
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EM6605 - 4 bit Microcontroller
Features
• Low Power - typical 4.0µA active mode
- typical 2.5µA standby mode
- typical 0.3µA sleep mode
@ 1.8V, 32kHz, 25 °C
• Low Voltage - 1.8 to 5.5V
• RC oscillator 30 - 300kHz
• buzzer - three tone
• ROM - 2k × 16 (Mask Programmed)
• RAM - 96 × 4 (User Read/Write)
• 2 clocks per instruction cycle
• RISC architecture
• 4 software configurable 4-bit ports
• Up to 16 inputs (4 ports)
• Up to 12 outputs (3 ports)
• Serial (Output) Write buffer - SWB
• Voltage level detection
• Analogue watchdog
• Timer watchdog
• 8 bit timer / event counter
• Internal interrupt sources (timer, event
counter, prescaler)
• External interrupt sources (portA + portC)
Description
The EM66XX series is an advanced single chip low
cost, mask programmed CMOS 4-bit microcontroller.
It contains ROM, RAM, watchdog timer, oscillation
detection circuit, combined timer / event counter,
prescaler, voltage level detector and a number of
clock functions. Its low voltage and low power
operation make it the most suitable controller for
battery, stand alone and mobile equipment. The
EM66XX series is manufactured using EM’s
Advanced Low Power CMOS Process.
Typical Applications
Figure 1.Architecture
Figure 2.Pin Configuration
• sensor interfaces
• domestic appliances
• security systems
• automotive controls
• TV & audio remote controls
• measurement equipment
• R/F and IR. control
© EM Microelectronic-Marin SA, 2/99, Rev. B/243
1
1 page  
1.Operating modes
EM6605
The EM6605 has two low power dissipation modes:
STANDBY and SLEEP. Figure 4 is a transition diagram
for these modes.
Figure 4.Mode Transition diagram
1.1.STANDBY Mode
Executing a HALT instruction puts the EM6605 into
STANDBY mode. The voltage regulator, oscillator,
Watchdog timer, interrupts and timer/event counter are
operating. However, the CPU stops since the clock
related to instruction execution stops. Registers, RAM,
and I/O pins retain their states prior to STANDBY mode.
STANDBY is cancelled by a RESET or an Interrupt
request if enabled.
Table 2 : shows the state of the EM6605 functions in
STANDBY and SLEEP modes.
Table 2.StandBy and Sleep Activities
1.2.SLEEP Mode
Writing to the SLEEP bit in the IntRq register puts the
EM6605 in SLEEP mode. The oscillator stops and most
functions of the EM6605 are inactive. To be able to write
the SLEEP bit, the SLmask bit must first be set to 1. In
SLEEP mode only the voltage regulator and RESET
input are active. The RAM data integrity is maintained.
SLEEP mode may be cancelled only by a RESET at the
terminal pin of the EM6605. The RESET must be high
for at least 2µsec.
FUNCTION
Oscillator
Instruction Execution
Registers and Flags
Interrupt Functions
RAM
Timer/Counter
Watchdog
I/O pins
Supply VLD
Reset pin
STANDBY
Active
Stopped
Retained
Active
Retained
Active
Active
Active
Stopped
Active
SLEEP
Stopped
Stopped
Reset
Stopped
Retained
Stopped
Stopped
High-Z or
Retained
Stopped
Active
Due to the cold start characteristics of the oscillator, waking up from SLEEP mode may take some time to
guarantee that the oscillator has started correctly. During this time the circuit is in RESET and the strobe
output STB/RST is high. Waking up from SLEEP mode clears the SLEEP flag but not the SLmask bit. By
reading SLmask one can therefore determine if the EM6605 was powered up (SLmask = 0), or woken
from SLEEP mode (SLmask = 1).
2.Power Supply
The EM6605 is supplied by a single external power supply between Vdd and Vss, the circuit reference
being at Vss (ground). A built-in voltage regulator generates Vreg providing regulated voltage for the
oscillator and internal logic. Output drivers are supplied directly from the external supply Vdd. A typical
connection configuration is shown in Figure 3.
For Vdd less then 2.0V it is recommended that Vdd is connected directly to Vreg
For Vdd>2.2V then the configuration shown in Fig.3 should be used.
© EM Microelectonic-Marin SA, 02/99, Rev. B/243
5
5 Page 
Debounced PA0 is connected to CPU TestVar1
Debounced PA1 is connected to CPU TestVar2
Debounced PA2 is connected to CPU TestVar3
Figure 6.Port A
EM6605
Additionally, PA3 can also be used as the input terminal for the event counter (see section 8).
The input port PA(0:3) also has individually selectable interrupts. Each port has its own interrupt mask bit in
the MPortA register. When an interrupt occurs inspection of the IRQpA and the IntRq registers allows the
source of the interrupt to be identified. The IRQpA register is automatically cleared by a RESET, by reading
the register. Reading IRQpA register also clears the INTPA flag in IntRq register. At initial RESET the
MPortA is set to 0, thus disabling any input interrupts.
See also section 9 for further details about the interrupt controller.
6.2.PortA registers
Table 12.PortA input status register - PortA
Bit Name
3 PA3
2 PA2
1 PA1
0 PA0
Reset
-
-
-
-
R/W
R
R
R
R
Description
PA3 input status
PA2 input status
PA1 input status
PA0 input status
Table 13.PortA Interrupt request register - IRQpA
Bit Name
Reset
R/W
3
IRQpa3
0
R
2
IRQpa2
0
R
1
IRQpa1
0
R
0
IRQpa0
0
R
Description
input PA3 interrupt request flag
input PA2 interrupt request flag
input PA1 interrupt request flag
input PA0 interrupt request flag
Table 14.PortA interrupt mask register - MportA
Bit Name
3 MPA3
2 MPA2
1 MPA1
0 MPA0
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
interrupt mask for input PA3
interrupt mask for input PA2
interrupt mask for input PA1
interrupt mask for input PA0
© EM Microelectonic-Marin SA, 02/99, Rev. B/243
11
11 Page | ||
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| PDF Descargar | [ Datasheet EM6605.PDF ] | |
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