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PDF HI7106 Data sheet ( Hoja de datos )
| Número de pieza | HI7106 | |
| Descripción | A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HI7106
July 1998
31/2 Digit, LCD/LED Display, A/D Converter
Features
• Guaranteed Zero Reading for 0V Input on All Scales
• True Polarity at Zero for Precise Null Detection
• 1pA Typical Input Current
• True Differential Input and Reference,
Direct Display Drive
• Low Noise - Less Than 15µVP-P
• On Chip Clock and Reference
• Low Power Dissipation - Typically Less Than 10mW
• No Additional Active Circuits Required
• Enhanced Display Stability
• Enhanced VCOM Reference Stability
Description
The Intersil HI7106 is a high performance, low power, 31/2
digit A/D converter. Included are seven segment decoders,
display drivers, a reference, and a clock. The HI7106 is
designed to interface with a liquid crystal display (LCD) and
includes a multiplexed backplane drive.
The HI7106 brings together a combination of high accuracy,
versatility, and true economy. It features auto-zero to less
than 10µV, zero drift of less than 1µV/oC, input bias current
of 10pA (Max), and rollover error of less than one count.
True differential inputs and reference are useful in all sys-
tems, but give the designer an uncommon advantage when
measuring load cells, strain gauges and other bridge type
transducers. Finally, the true economy of single power supply
operation enables a high performance panel meter to be built
with the addition of only 10 passive components and a display.
Ordering Information
PART NO.
HI7106CPL
HI7106CM44
HI7106C/D
TEMP.
RANGE (oC)
PACKAGE
0 to 70 40 Ld PDIP
0 to 70 44 Ld MQFP
0 to 70 DIE
PKG. NO.
E40.6
Q44.10x10
Pinouts
HI7106
(PDIP)
TOP VIEW
V+
D1
C1
B1
(1’s) A1
F1
G1
E1
D2
C2
B2
(10’s)
A2
F2
E2
D3
B3
(100’s)
F3
E3
(1000) AB4
(MINUS) POL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 OSC 1
39 OSC 2
38 OSC 3
37 TEST
36 REF HI
35 REF LO
34 CREF+
33 CREF-
32 COMMON
31 IN HI
30 IN LO
29 A-Z
28 BUFF
27 INT
26 V-
25 G2 (10’s)
24 C3
23 A3 (100’s)
22 G3
21 BP/GND
HI7106
(MQFP)
TOP VIEW
NC
NC
TEST
OSC 3
NC
OSC 2
OSC 1
V+
D1
C1
B1
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
NC
G2
C3
A3
G3
BP/GND
POL
AB4
E3
F3
B3
A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 4551
1 page  
HI7106
De-Integrate Phase
The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
output to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
DISPLAY
COUNT
=
1000
V---V--R---I-EN----F-
.
Differential Input
The input can accept differential voltages anywhere within
the common mode range of the input amplifier, or specifically
from 0.5V below the positive supply to 1V above the
negative supply. In this range, the system has a CMRR of
86dB typical. However, care must be exercised to assure the
integrator output does not saturate. A worst case condition
would be a large positive common mode voltage with a near
full scale negative differential input voltage. The negative
input signal drives the integrator positive when most of its
swing has been used up by the positive common mode
voltage. For these critical applications the integrator output
swing can be reduced to less than the recommended 2V full
scale swing with little loss of accuracy. The integrator output
can swing to within 0.3V of either supply without loss of
linearity.
Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The same holds true for the reference voltage. If
reference can be conveniently tied to analog COMMON, it
should be since this removes the common mode voltage
from the reference system.
Within the lC, analog COMMON is tied to an N-Channel FET
that can sink approximately 30mA of current to hold the
voltage 2.8V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
10µA of source current, so COMMON may easily be tied to a
more negative voltage thus overriding the internal reference.
V
REF HI
REF LO
HI7106
V+
6.8V
ZENER
IZ
Differential Reference
The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity
on its nodes. If there is a large common mode voltage, the
reference capacitor can gain charge (increase voltage) when
called up to de-integrate a positive signal but lose charge
(decrease voltage) when called up to de-integrate a negative
input signal. This difference in reference for positive or
negative input voltage will give a roll-over error. However, by
selecting the reference capacitor such that it is large enough
in comparison to the stray capacitance, this error can be
held to less than 0.5 count worst case. (See Component
Value Selection.)
Analog COMMON
This pin is included primarily to set the common mode voltage
for battery operation or for any system where the input signals
are floating with respect to the power supply. The COMMON
pin sets a voltage that is approximately 2.8V more negative
than the positive supply. This is selected to give a minimum
end-of-life battery voltage of about 6V. However, analog COM-
MON has some of the attributes of a reference voltage. When
the total supply voltage is large enough to cause the zener to
regulate (>7V), the COMMON voltage will have a low voltage
coefficient (0.001%/V), low output impedance (≅15Ω), and a
temperature coefficient typically less than 80ppm/oC. An exter-
nal reference can easily be added, as shown in Figure 3.
V-
FIGURE 3A.
V+
V
HI7106
20kΩ
6.8kΩ
REF HI
REF LO
COMMON
ICL8069
1.2V
REFERENCE
FIGURE 3B.
FIGURE 3. USING AN EXTERNAL REFERENCE
TEST
The TEST pin serves two functions. On the HI7106 it is cou-
pled to the internally generated digital supply through a
500Ω resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal points
or any other presentation the user may want to include on
the LCD display. Figures 4 and 5 show such an application.
No more than a 1mA load should be applied.
5
5 Page 
HI7106
Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
-A-
E E1
PIN 1
-H-
0.40
0.016 MIN
0o MIN
0o-7o
L
D
D1
-D-
-B-
e
SEATING
A PLANE
5o-16o
A2 A1
0.10
0.004
-C-
0.20
0.008
M
C
A-B S
DS
B
B1
5o-16o
0.13/0.17
0.005/0.007
BASE METAL
WITH PLATING
0.13/0.23
0.005/0.009
Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
SYM-
BOL
INCHES
MIN MAX
MILLIMETERS
MIN MAX
NOTES
A
-
0.093
-
2.35
-
A1
0.004 0.010 0.10
0.25
-
A2
0.077 0.083 1.95
2.10
-
B
0.012 0.018 0.30
0.45
6
B1
0.012 0.016 0.30
0.40
-
D 0.510 0.530 12.95 13.45
3
D1 0.390 0.398 9.90 10.10 4, 5
E 0.510 0.530 12.95 13.45
3
E1 0.390 0.398 9.90 10.10 4, 5
L
0.026 0.037 0.65
0.95
-
N 44
44 7
e 0.032 BSC
0.80 BSC
-
Rev. 1 1/94
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
11
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| PDF Descargar | [ Datasheet HI7106.PDF ] | |
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