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PDF CA3310 Data sheet ( Hoja de datos )
| Número de pieza | CA3310 | |
| Descripción | A/D Converters | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CA3310 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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CA3310, CA3310A
May 2001
File Number 3095.3
CMOS, 10-Bit, A/D Converters with
Internal Track and Hold
The Intersil CA3310 is a fast, low power, 10-bit successive
approximation analog-to-digital converter, with
microprocessor-compatible outputs. It uses only a single 3V
to 6V supply and typically draws just 3mA when operating at
5V. It can accept full rail-to-rail input signals, and features a
built-in track and hold. The track and hold will follow high
bandwidth input signals, as it has only a 100ns (typical) input
time constant.
The ten data outputs feature full high-speed CMOS three-
state bus driver capability, and are latched and held through
a full conversion cycle. Separate 8 MSB and 2 LSB enables,
a data ready flag, and conversion start and ready reset
inputs complete the microprocessor interface.
An internal, adjustable clock is provided and is available as
an output. The clock may also be driven from an external
source.
Part Number Information
PART LINEARITY
NUMBER (INL, DNL)
TEMP.
RANGE
(oC)
PACKAGE
PKG.
NO.
CA3310E ±0.75 LSB -40 to 85 24 Ld PDIP E24.6
CA3310M ±0.75 LSB -40 to 85 24 Ld SOIC M24.3
CA3310AM ±0.5 LSB -40 to 85 24 Ld SOIC M24.3
Features
• CMOS Low Power (Typ) . . . . . . . . . . . . . . . . . . . . . 15mW
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3V to 6V
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13µs
• Built-In Track and Hold
• Rail-to-Rail Input Range
• Latched Three-state Output Drivers
• Microprocessor-Compatible Control Lines
• Internal or External Clock
Applications
• Fast, No-Droop, Sample and Hold
• Voice Grade Digital Audio
• DSP Modems
• Remote Low Power Data Acquisition Systems
• µP Controlled Systems
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinout
CA3310, CA3310A
(PDIP, SOIC)
TOP VIEW
D0 (LSB) 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
D8 9
D9 (MSB) 10
DRDY 11
VSS (GND) 12
24 VDD
23 VIN
22 VREF +
21 REXT
20 CLK
19 STRT
18 VREF -
17 VAA+
16 VAA-
15 OEL
14 OEM
13 DRST
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1 page  
CA3310, CA3310A
Electrical Specifications TA = 25×oC, VDD = VAA+ = 5V, VREF+ = 4.608V, VSS = VAA- = VREF- = GND, CLK = External 1MHz, Unless
Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
CLK OUTPUT
High-Level Output Voltage
Low-Level Output Voltage
TIMING
ISOURCE = 100µA (Note 3)
ISlNK = 100µA (Note 3)
Clock Frequency
Internal, CLK and REXT Open
Internal, CLK Shorted to REXT
External, Applied to CLK (Note 3)
(Max)
(Min)
Clock Pulse Width, tLOW, tHIGH
External, Applied to CLK:
See Figure 1 (Note 3)
Conversion Time
Aperture Delay, tD APR
Clock to Data Ready Delay, tD1 DRDY
Clock to Data Ready Delay, tD2 DRDY
Clock to Data Delay, tD Data
Start Removal Time, tR STRT
Start Setup Time, tSU STRT
Start Pulse Width, tW STRT
Start to Data Ready Delay, tD3 DRDY
Clock Delay from Start, tD CLK
Ready Reset Removal Time, tR DRST
Ready Reset Pulse Width, tW DRST
Ready Reset to Data Ready Delay,
tD4 DRDY
Output Enable Delay, tEN
Output Disable Delay, tDIS
SUPPLIES
Internal, CLK Shorted to REXT
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figures 3 and 4 (Note 2)
See Figure 4
See Figures 3 and 4
See Figures 3 and 4
See Figure 3
See Figure 5 (Note 2)
See Figure 5
See Figure 5
See Figure 2
See Figure 2
Supply Operating Range, VDD or VAA
Supply Current, IDD + IAA
Supply Standby Current
(Note 3)
See Figures 14, 15
Clock Stopped During Cycle 1
Analog Supply Rejection
At 120Hz, See Figure 13
Reference Input Current
See Figure 10
TEMPERATURE DEPENDENCY
Offset Drift
At 0 to 1 Code Transition
Gain Drift
At 1022 to 1023 Code Transition
Internal Clock Speed
See Figure 7
NOTES:
2. A (-) removal time means the signal can be removed after the reference signal.
3. Parameter not tested, but guaranteed by design or characterization.
MIN
4
-
200
600
-
100
100
13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
-
-
-
-
-
-
-
TYP
-
-
300
800
4
10
-
-
100
150
250
200
-120
160
10
170
200
- 80
10
35
40
50
-
3
3.5
25
160
-4
-6
-0.5
MAX
-
1
400
1000
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
8
-
-
-
-
-
-
UNITS
V
V
kHz
kHz
MHz
kHz
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
mA
mA
mV/ V
µA
µV/ oC
µV/ oC
% /oC
5
5 Page 
CA3310, CA3310A
period 1, and is not reapplied during that period, the clock
will shut off after entering period 2. The input will continue to
track the DRDY output will remain high during this time.
A low signal applied to STRT (at least tW STRT wide) can
now initiate a new conversion. The STRT signal (after a
delay of tD3 DRDY) will cause the DRDY flag to drop, and
(after a delay of tD CLK) cause the clock to restart.
Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.
The input will continue to track until the end of period 3, the
same as when free-running.
Figure 4 illustrates the same operation as above, but with an
external clock. If STRT is removed (at least tR STRT) before
clock period 1, and not reapplied during that period, the
clock will continue to cycle in period 2. A low signal applied
to STRT will drop the DRDY flag as before, and with the first
positive-going clock edge that meets the tSU STRT set-up
time, the converter will continue with clock period 3.
The DRDY flag output, as described previously, goes active
at the start of period 1, and drops at the start of period 2 or
upon a new STRT command, whichever is later. It may also
be controlled with the DRST (Data Ready Reset) input.
Figure 5 depicts this operation.
DRST must be removed (at least tR DRST) before the start of
period 1 to allow DRDY to go high. A low level on DRST (at least
tW DRST wide) will (after a delay of tD4 DRDY) drop DRDY.
Analog Input
The analog input pin is a predominantly capacitive load that
changes between the track and hold periods of a conversion
cycle. During hold, clock period 4 through 13, the input
loading is leakage and stray capacitance, typically less than
0.1µA and 20pF.
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have
low enough impedance to dissipate the charge by the end of
the tracking period. The amount of charge is dependent on
supply and input voltages. Figure 8 shows typical peak input
currents for various supply and input voltages, while Figure 9
shows typical average input currents. The average current is
also proportional to clock frequency, and should be scaled
accordingly.
During tracking, the input appears as approximately a 300pF
capacitor in series with 330Ω, for a 100ns time constant. A
full-scale input swing would settle to 1/2 LSB (1/2048) in 7RC
time constants. Doing continuous conversions with a 1MHz
clock provides 3µs of tracking time, so up to 1kΩ of external
source impedance (400ns time constant) would allow proper
settling of a step input.
If the clock was slower, or the converter was not restarted
immediately (causing a longer sample lime), a higher source
impedance could be used.
The CA3310s low-input time constant also allows good
tracking of dynamic input waveforms. The sampling rate with
a 1MHz clock is approximately 80kHz. A Nyquist rate
(fSAMPLE/2) input sine wave of 40kHz would have negligible
attenuation and a phase lag of only 1.5 degrees.
Accuracy Specifications
The CA3310 accepts an analog input between the values of
VREF- and VREF+, and quantizes it into one of 210 or 1024
output codes. Each code should exist as the input is varied
through a range of 1/1024 x (VREF+ - VREF-), referred to as
1 LSB of input voltage. A differential Iinearity error, illustrated in
Figure 17, occurs if an output code occurs over other than the
ideal (1 LSB) input range. Note that as long as the error does
not reach -1 LSB, the converter will not miss any codes.
OUTPUT
CODE
UNIFORM
TRANSFER
CURVE
A
B
C
ACTUAL
TRANSFER
CURVE
A = IDEAL 1 LSB STEP
B-A = + DIFFERENTIAL LINEARITY ERROR
A-C = - DIFFERENTIAL LINEARITY ERROR
INPUT VOLTAGE
FIGURE 17. DIFFERENTIAL LINEARITY ERROR
The CA3310 output should change from a code of 00016 to
00116 at an input voltage of (VREF- +1 LSB). It should also
change from a code of 3FE16 to 3FF16 at an input of
(VREF + -1 LSB). Any differences between the actual and
expected input voltages that cause these transitions are
the offset and gain errors, respectively. Figure 18 illustrates
these errors.
As the input voltage is increased linearly from the point that
causes the 00016 to 00116 transition to the point that
causes the 3FE16 to 3FF16 transition, the output code
should also increase linearly. Any deviation from this
input-to-output correspondence is integral linearity error,
illustrated in Figure 19.
Note that the integral linearity is referenced to a straight line
drawn through the actual end points, not the ideal end points.
For absolute accuracy to be equal to the integral linearity, the
gain and offset would have to be adjusted to ideal.
Offset and Gain Adjustments
The VREF+ and VREF- pins, references for the two ends of
the analog input range, are the only means of doing offset or
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CA3310.PDF ] | |
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