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PDF DS40MB200 Data sheet ( Hoja de datos )
| Número de pieza | DS40MB200 | |
| Descripción | Dual 4 Gb/s 1:2 Mux/Buffer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 2005
DS40MB200
Dual 4 Gb/s 1:2 Mux/Buffer with Input Equalization and
Output Pre-Emphasis
General Description
The DS40MB200 is a dual signal conditioning 2:1 multi-
plexer and 1:2 fan-out buffer designed for use in backplane
redundancy applications. Signal conditioning features in-
clude input equalization and programmable output pre-
emphasis that enable data communication in FR4 back-
planes up to 4 Gb/s. Each input stage has a fixed equalizer
to reduce ISI distortion from board traces. All output drivers
have 4 selectable steps of pre-emphasis to compensate for
transmission losses from long FR4 backplanes and reduce
deterministic jitter. The pre-emphasis levels can be indepen-
dently controlled for the line-side and switch-side drivers.
The internal loopback paths from switch-side input to switch-
side output enable at-speed system testing. All receiver
inputs and driver outputs are internally terminated with 100Ω
differential terminating resistors
Features
n Dual 2:1 multiplexer and 1:2 buffer
n 1– 4 Gbps fully differential data paths
n Fixed input equalization
n Programmable output pre-emphasis
n Independent switch and line side pre-emphasis controls
n Programmable switch-side loopback mode
n On-chip terminations
n +3.3V supply
n Low power, 1W max
n ESD rating HBM 6 kV
n Lead-less LLP-48 package (7mmx7mmx0.8mm, 0.5mm
pitch)
n 0˚C to +85˚C operating temperature range
Functional Block Diagram
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© 2005 National Semiconductor Corporation DS200217
20021733
www.national.com
1 page  
Pin Descriptions (Continued)
Pin Name
POWER
VCC
Pin
Number
2, 8, 14,
20, 29, 35,
38, 44
I/O
P
GND
GND
5, 11, 17,
32, 41
DAP
P
P
Note: I = Input, O = Output, P = Power
Description
VCC = 3.3V ± 5%.
Each VCC pin should be connected to the VCC plane through a low inductance path,
typically with a via located as close as possible to the landing pad of the VCC pin.
It is recommended to have a 0.01 µF or 0.1 µF, X7R, size-0402 bypass capacitor from
each VCC pin to ground plane.
Ground reference. Each ground pin should be connected to the ground plane through a low
inductance path, typically with a via located as close as possible to the landing pad of the
GND pin.
Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the
LLP-48 package. It should be connected to the GND plane with at least 4 via to lower the
ground impedance and improve the thermal performance of the package.
Functional Description
The DS40MB200 is a signal conditioning 2:1 multiplexer and
a 1:2 buffer designed to support port redundancy up to 4
Gb/s. Each input stage has a fixed equalizer that provides
equalization to compensate about 5 dB of transmission loss
from a short backplane trace (about 10 inches backplane).
The output driver has pre-emphasis (driver-side equaliza-
tion) to compensate the transmission loss of the backplane
that it is driving. The driver conditions the output signal such
that the lower frequency and higher frequency pulses reach
approximately the same amplitude at the end of the back-
plane, and minimize the deterministic jitter caused by the
amplitude disparity. The DS40MB200 provides 4 steps of
user-selectable pre-emphasis ranging from 0, -3, -6 and –9
dB to handle different lengths of backplane. Figure 1 shows
a driver pre-emphasis waveform. The pre-emphasis duration
is 200ps nominal, corresponds to 0.75 bit-width at 4 Gb/s.
The pre-emphasis levels of switch-side and line-side can be
individually programmed.
The high speed inputs are self-biased to about 1.5V and are
designed for AC coupling. The inputs are compatible to most
AC coupling differential signals such as LVDS, LVPECL and
CML.
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TABLE 1. LOGIC TABLE FOR MULTIPLEX CONTROLS
MUX_S0
0
1 (default)
MUX_S1
0
1 (default)
Mux Function
MUX_0 select switch_B input, SIB_0±.
MUX_0 select switch_A input, SIA_0±.
Mux Function
MUX_1 select switch_B input, SIB_1±.
MUX_1 select switch_A input, SIA_0±.
TABLE 2. LOGIC TABLE FOR LOOPBACK Controls
LB0A
0
1 (default)
LB0B
0
1 (default)
LB1A
0
1 (default)
LB1B
0
1 (default)
Loopback Function
Enable loopback from SIA_0± to SOA_0±.
Normal mode. Loopback disabled.
Loopback Function
Enable loopback from SIB_0± to SOB_0±.
Normal mode. Loopback disabled.
Loopback Function
Enable loopback from SIA_1± to SOA_1±.
Normal mode. Loopback disabled.
Loopback Function
Enable loopback from SIB_1± to SOB_1±.
Normal mode. Loopback disabled.
5 www.national.com
5 Page 
Timing Diagrams (Continued)
Trace Length
25 inches
Finished Trace
Width W
8.5 mil
Separation between
Dielectric Constant
Traces
Dielectric Height H
eR
11.5 mil
6 mil
3.8
Loss Tangent
0.022
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FIGURE 6. Data input and output eye patterns with driver set to 0 dB pre-emphasis
20021742
11 www.national.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DS40MB200.PDF ] | |
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