DataSheetWiki


SCANPSC110F fiches techniques PDF

Fairchild Semiconductor - SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port

Numéro de référence SCANPSC110F
Description SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





1 Page

No Preview Available !





SCANPSC110F fiche technique
March 1993
Revised August 2000
SCANPSC110F
SCAN Bridge Hierarchical and Multidrop Addressable
JTAG Port (IEEE1149.1 System Test Support)
General Description
The SCANPSC110F Bridge extends the IEEE Std. 1149.1
test bus into a multidrop test bus environment. The advan-
tage of a hierarchical approach over a single serial scan
chain is improved test throughput and the ability to remove
a board from the system and retain test access to the
remaining modules. Each SCANPSC110F Bridge supports
up to 3 local scan rings which can be accessed individually
or combined serially. Addressing is accomplished by load-
ing the instruction register with a value matching that of the
Slot inputs. Backplane and inter-board testing can easily
be accomplished by parking the local TAP Controllers in
one of the stable TAP Controller states via a Park instruc-
tion. The 32-bit TCK counter enables built in self test oper-
ations to be performed on one port while other scan chains
are simultaneously tested.
Features
s True IEEE1149.1 hierarchical and multidrop addressable
capability
s The 6 slot inputs support up to 59 unique addresses, a
Broadcast Address, and 4 Multi-cast Group Addresses
s 3 IEEE 1149.1-compatible configurable local scan ports
s Mode Register allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or
serially in groups of two or three
s 32-bit TCK counter
s 16-bit LFSR Signature Compactor
s L4
s local TAPs can be 3-stated via the OE input to allow an
alternate test master to take control of the local TAPs
Ordering Code:
Order Number Package Number
Package Description
SCANPSC110FSC
M28B
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin
Names
Description
TCKB
TMSB
TDIB
TDOB
TRST
Backplane Test Clock Input
Backplane Test Mode Select Input
Backplane Test Data Input
Backplane Test Data Output
Asynchronous Test Reset Input (Active LOW)
S(0,5)
OE
Address Select Port
Local Scan Port Output Enable (Active LOW)
TCKL(13) Local Port Test Clock Output
TMSL(13) Local Port Test Mode Select Output
TDIL(13) Local Port Test Data Input
TDOL(13) Local Port Test Data Output
© 2000 Fairchild Semiconductor Corporation DS011570
www.fairchildsemi.com

PagesPages 25
Télécharger [ SCANPSC110F ]


Fiche technique recommandé

No Description détaillée Fabricant
SCANPSC110 SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) National Semiconductor
National Semiconductor
SCANPSC110F SCAN Bridge Hierarch Multidrop Addres JTAG Prt IEEE1149.1 Sys Tst Spprt (Rev. D) Texas Instruments
Texas Instruments
SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port National Semiconductor
National Semiconductor
SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port Fairchild Semiconductor
Fairchild Semiconductor

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche