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PDF AD9861 Data sheet ( Hoja de datos )
| Número de pieza | AD9861 | |
| Descripción | Mixed-Signal Front-End (MxFE-TM) Baseband Transceiver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Mixed-Signal Front-End (MxFE™) Baseband
Transceiver for Broadband Applications
AD9861
FEATURES
Receive path includes dual 10-bit analog-to-digital
converters with internal or external reference, 50 MSPS
and 80 MSPS versions
Transmit path includes dual 10-bit, 200 MSPS digital-to-
analog converters with 1×, 2×, or 4× interpolation and
programmable gain control
Internal clock distribution block includes a programmable
phase-locked loop and timing generation circuitry,
allowing single-reference clock operation
20-pin flexible I/O data interface allows various interleaved
or noninterleaved data transfers in half-duplex mode and
interleaved data transfers in full-duplex mode
Configurable through register programmability or
optionally limited programmability through mode pins
Independent Rx and Tx power-down control pins
64-lead LFCSP package (9 mm × 9 mm footprint)
3 configurable auxiliary converter pins
APPLICATIONS
Broadband access
Broadband LAN
Communications (modems)
GENERAL DESCRIPTION
The AD9861 is a member of the MxFE family—a group of
integrated converters for the communications market. The
AD9861 integrates dual 10-bit analog-to-digital converters
(ADC) and dual 10-bit digital-to-analog converters (TxDAC®).
Two speed grades are available, -50 and -80. The -50 is opti-
mized for ADC sampling of 50 MSPS and less, while the -80 is
optimized for ADC sample rates between 50 MSPS and 80 MSPS.
The dual TxDACs operate at speeds up to 200 MHz and
include a bypassable 2× or 4× interpolation filter. Three
auxiliary converters are also available to provide required
system level control voltages or to monitor system signals. The
AD9861 is optimized for high performance, low power, small
form factor, and to provide a cost-effective solution for the
broadband communication market.
The AD9861 uses a single input clock pin (CLKIN) to generate
all system clocks. The ADC and TxDAC clocks are generated
within a timing generation block that provides user programma-
ble options such as divide circuits, PLL multipliers, and switches.
A flexible, bidirectional 20-bit I/O bus accommodates a variety
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
VIN+A
VIN–A
VIN+B
VIN–B
IOUT+A
IOUT–A
IOUT+B
IOUT–B
FUNCTIONAL BLOCK DIAGRAM
ADC
ADC
DATA
MUX
AND
LATCH
Rx DATA
DAC
DAC
LOW-PASS
INTERPOLATION
FILTER
I/O
INTERFACE
CONFIGURATION
BLOCK
DATA
LATCH
AND
DEMUX
Tx DATA
I/O
INTERFACE
CONTROL
FLEXIBLE
I/O BUS
[0:19]
AUX
ADC
AUX
DAC
AUX
DAC
AUX
ADC
AUX
DAC
ADC CLOCK
DAC CLOCK
PLL
AD9861
CLKIN
Figure 1.
03606-0-001
of custom digital back ends or open market DSPs.
In half-duplex systems, the interface supports 20-bit parallel
transfers or 10-bit interleaved transfers. In full-duplex systems,
the interface supports an interleaved 10-bit ADC bus and an
interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin
count and, therefore, reduces the required package size on the
AD9861 and the device to which it connects.
The AD9861 can use either mode pins or a serial program-
mable interface (SPI) to configure the interface bus, operate the
ADC in a low power mode, configure the TxDAC interpolation
rate, and control ADC and TxDAC power-down. The SPI
provides more programmable options for both the TxDAC path
(for example, coarse and fine gain control and offset control for
channel matching) and the ADC path (for example, the internal
duty cycle stabilizer, and twos complement data format).
The AD9861 is packaged in a 64-lead LFCSP (low profile, fine
pitched, chip scale package). The 64-lead LFCSP footprint is
only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into
tightly spaced applications such as PCMCIA cards
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
POWER SPECIFICATIONS
Table 3. AD9861-50 and AD9861-80
Analog and digital supplies = 3.3 V; FCLKIN = 50 MHz; PLL 4× setting; normal timing mode
Parameter
Temp
Test Level
POWER SUPPLY RANGE
Analog Supply Voltage (AVDD)
Digital Supply Voltage (DVDD)
Driver Supply Voltage (DRVDD)
Full IV
Full IV
Full IV
ANALOG SUPPLY CURRENTS
TxPath (20 mA Full-Scale Outputs)
Full V
TxPath (2 mA Full-Scale Outputs)
Full V
Rx Path (-80, at 80 MSPS)
Full V
RxPath (-80, at 40 MSPS, Low Power Mode)
RxPath (-80, at 20 MSPS, Ultralow Power Mode)
Rx Path (-50, at 50 MSPS)
RxPath (-50, at 50 MSPS, Low Power Mode)
Full V
Full V
Full V
Full V
RxPath (-50, at 16 MSPS, Ultralow Power Mode)
Full V
TxPath, Power-Down Mode
Full V
RxPath, Power-Down Mode
Full V
PLL Full V
DIGITAL SUPPLY CURRENTS
TxPath, 1× Interpolation,
50 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
TxPath, 2× Interpolation,
100 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
TxPath, 4× Interpolation,
Full V
Full V
Full V
200 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
RxPath Digital, Half-Duplex 24 Mode
Full V
AD9861
Min Typ Max Unit
2.7 3.6 V
2.7 3.6 V
2.7 3.6 V
70 mA
20 mA
165 mA
82 mA
35 mA
103 mA
69 mA
28 mA
2 mA
5 mA
12 mA
20 mA
50 mA
80 mA
15 mA
DIGITAL SPECIFICATIONS
Table 4. AD9861-50 and AD9861-80
Parameter
LOGIC LEVELS
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Output Logic High Voltage, VOH (1 mA Load)
Output Logic Low Voltage, VOL (1 mA Load)
DIGITAL PIN
Input Leakage Current
Input Capacitance
Minimum RESET Low Pulse Width
Digital Output Rise/Fall Time
Temp Test Level Min
Typ Max Unit
Full IV
Full IV
Full IV
Full IV
DRVDD – 0.7
DRVDD – 0.6
V
0.4 V
V
0.4 V
Full IV
Full IV
Full IV
Full IV
5
2.8
12 µA
3 pF
Input Clock Cycles
4 ns
Rev. 0 | Page 5 of 52
5 Page 
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
5 10 15 20 25
FREQUENCY (MHz)
Figure 10. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path
Digitizing 76 MHz Tone
62
NORMAL POWER @ 50MSPS
LOW POWER ADC @ 25MSPS
59
56
ULTRALOW POWER ADC
@ 16MSPS
53
50
0 5 10 15 20 25
INPUT FREQUENCY (MHz)
Figure 11. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone
SNR Performance vs. Input Frequency
80
LOW POWER ADC @ 25MSPS
75
70 NORMAL POWER @ 50MSPS
65
60
ULTRALOW POWER ADC
@ 16MSPS
55
50
0 5 10 15 20 25
INPUT FREQUENCY (MHz)
Figure 12. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone
SFDR Performance vs. Input Frequency
AD9861
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
5 10 15 20 25
FREQUENCY (MHz)
Figure 13. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path
Digitizing 70 MHz and 72 MHz Tones
62
NORMAL POWER @ 50MSPS
10.0
9.8
LOW POWER ADC @ 25MSPS
59
9.6
9.4
9.2
56 9.0
ULTRALOW POWER ADC
@ 16MSPS
53
8.8
8.6
8.4
8.2
50 8.0
0 5 10 15 20 25
INPUT FREQUENCY (MHz)
Figure 14. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone
SINAD Performance vs. Input Frequency
–50
–55
–60
ULTRALOW POWER ADC
@ 16MSPS
–65
NORMAL POWER @ 50MSPS
–70
–75
LOW POWER ADC @ 25MSPS
–80
0
5 10 15 20 25
INPUT FREQUENCY (MHz)
Figure 15. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone
THD Performance vs. Input Frequency
Rev. 0 | Page 11 of 52
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9861.PDF ] | |
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