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PDF FDMA2002NZ Data sheet ( Hoja de datos )
| Número de pieza | FDMA2002NZ | |
| Descripción | Dual N-Channel PowerTrench MOSFET | |
| Fabricantes | Fairchild Semiconductor | |
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May 2006
May 2006
FDMA2002NZ
Dual N-Channel PowerTrench® MOSFET
General Description
This device is designed specifically as a single package
solution for dual switching requirements in cellular
handset and other ultra-portable applications. It
features two independent N-Channel MOSFETs with
low on-state resistance for minimum conduction losses.
The MicroFET 2x2 offers exceptional thermal
performance for its physical size and is well suited to
linear mode applications.
Features
• 2.9 A, 30 V RDS(ON) = 123 mΩ @ VGS = 4.5 V
RDS(ON) = 140 mΩ @ VGS = 3.0 V
RDS(ON) = 163 mΩ @ VGS = 2.5 V
• Low profile – 0.8 mm maximum – in the new package
MicroFET 2x2 mm
• RoHS Compliant
PIN 1
S1 G1 D2
D1 D2
D1 G2 S2
MicroFET 2x2
www.DataSheet4U.com
S1 1
G1 2
D2 3
6 D1
5 G2
4 S2
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
VDS
VGS
ID
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous (TC = 25°C, VGS = 4.5V)
– Continuous (TC = 25°C, VGS = 2.5V)
– Pulsed
PD Power Dissipation for Single Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
TJ, TSTG
Operating and Storage Temperature
Ratings
30
±12
2.9
2.7
10
1.5
0.65
–55 to +150
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
RθJA Thermal Resistance, Junction-to-Ambient
RθJA Thermal Resistance, Junction-to-Ambient
RθJA Thermal Resistance, Junction-to-Ambient
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1d)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
002
FDMA2002NZ
7’’
83 (Single Operation)
193 (Single Operation)
68 (Dual Operation)
145 (Dual Operation)
Tape width
8mm
Units
V
V
A
W
°C
°C/W
Quantity
3000 units
©2006 Fairchild Semiconductor Corporation
FDMA2002NZ Rev B(W)
1 page  
Typical Characteristics
10
ID = 2.9A
8
6
4
VDS = 10V
20V
15V
2
0
0123456
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
100
10
RDS(ON) LIMIT
1
100us
10ms 1ms
100ms
1s
10s
DC
VGS = 4.5V
0.1 SINGLE PULSE
RθJA = 193oC/W
TA = 25oC
0.01
0.1
1 10
VDS, DRAIN-SOURCE VOLTAGE (V)
100
Figure 9. Maximum Safe Operating Area.
300
f = 1MHz
VGS = 0 V
250
200
Ciss
150
100
50
Crss
0
0
Coss
5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure 8. Capacitance Characteristics.
15
SINGLE PULSE
RθJA = 193°C/W
12 TA = 25°C
9
6
3
0
0.0001 0.001 0.01
0.1
1
10 100 1000
t1, TIME (sec)
Figure 10. Single Pulse Maximum Power
Dissipation.
1
D = 0.5
0.1
0.01
0.0001
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
0.001
0.01
0.1
t1, TIME (sec)
1
RθJA(t) = r(t) * RθJA
RθJA =193°C/W
P(pk)
t1
t2
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
10 100 1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDMA2002NZ Rev B(W)
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet FDMA2002NZ.PDF ] | |
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