PDF AD9979 Data sheet ( Hoja de datos )

Número de pieza	AD9979
Descripción	CCD Signal Processor
Fabricantes	Analog Devices
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No Preview Available ! 14-Bit, CCD Signal Processor with Precision Timing Core AD9979 FEATURES 1.8 V analog and digital core supply voltage Correlated double sampler (CDS) with –3 dB, 0 dB, +3 dB, and +6 dB gain 6 dB to 42 dB 10-bit variable gain amplifier (VGA) 14-bit 65 MHz analog-to-digital converter Black-level clamp with variable level control Complete on-chip timing generator Precision Timing™ core with 240 ps resolution @ 65 MHz On-chip 3 V horizontal and RG drivers General-purpose outputs (GPOs) for shutter and system support 7 mm × 7 mm, 48-lead LFCSP Internal LDO regulator circuitry APPLICATIONS Professional HDTV camcorders Professional/high end digital cameras Broadcast cameras Industrial high speed cameras GENERAL DESCRIPTION The AD9979 is a highly integrated CCD signal processor for high speed digital video camera applications. Specified at pixel rates of up to 65 MHz, the AD9979 consists of a complete analog front end with analog-to-digital conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with approximately 240 ps resolution at 65 MHz operation. The analog front end includes black-level clamping, CDS, VGA, and a 65 MSPS, 14-bit analog-to-digital converter (ADC). The timing driver provides the high speed CCD clock drivers for RG, HL, and H1 to H4. Operation is programmed using a 3-wire serial interface. Available in a space-saving, 7 mm × 7 mm, 48-lead LFCSP, the AD9979 is specified over an operating temperature range of −25°C to +85°C. CCDINP CCDINM FUNCTIONAL BLOCK DIAGRAM REFT REFB AD9979 VREF CDS VGA –3dB, 0dB, +3dB, +6dB 6dB TO 42dB ADC CLAMP 14 DOUT D0 TO D13 LDOOUT LDO RG HL H1 TO H4 4 HORIZONTAL DRIVERS GPO1 GPO2 INTERNAL CLOCKS PRECISION TIMING CORE SYNC GENERATOR HD VD Figure 1. INTERNAL REGISTERS SL SCK SDI CLI Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved. 1 page AD9979 DIGITAL SPECIFICATIONS IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD = 2.7 V to 3.6 V, CL = 20 pF, tMIN to tMAX, unless otherwise noted. Table 3. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage CLI INPUT (CLI_BIAS = 0) High Level Input Voltage Low Level Input Voltage H-DRIVER OUTPUTS High Level Output Voltage at Maximum Current Low Level Output Voltage at Maximum Current Maximum Output Current (Programmable) Maximum Load Capacitance Symbol Min Typ Max Test Conditions/ Unit Comments VIH IOVDD − 0.6 VIL 0.6 IIH 10 IIL 10 CIN 10 V V μA μA pF VOH IOVDD − 0.5 VOL 0.5 V IOH = 2 mA V IOL = 2 mA VIHCLI VILCLI IOVDD/2 + 0.5 V IOVDD/2 − 0.5 V VOH HVDD − 0.5 VOL 0.5 30 100 V V mA pF Rev. C \| Page 5 of 56 5 Page EQUIVALENT INPUT/OUTPUT CIRCUITS AVDD R AVSS AVSS Figure 8. CCD Input IOVDD 330Ω AD9979 DATA DVSS Figure 10. Digital Inputs HVDD OR RGVDD IOVDD CLI 330Ω 100kΩ + AVSS Figure 9. CLI Input, Register 0x15[0] =1 Enables the Bias Circuit ENABLE OUTPUT HVSS OR RGVSS Figure 11. H1 to H4, HL, and RG Outputs Rev. C \| Page 11 of 56 11 Page

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