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PDF AD8375 Data sheet ( Hoja de datos )
| Número de pieza | AD8375 | |
| Descripción | Ultralow Distortion IF VGA | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8375 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
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Data Sheet
FEATURES
Bandwidth of 630 MHz (−3 dB)
Gain range: −4 dB to +20 dB
Step size: 1 dB ± 0.2 dB
Differential input and output
Noise figure: 8 dB @ maximum gain
Output IP3 of ~50 dBm at 200 MHz
Output P1dB of 19 dBm at 200 MHz
Provides constant SFDR vs. gain
Parallel 5-bit control interface
Power-down feature
Single 5 V supply operation
24-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Differential ADC drivers
High IF sampling receivers
Wideband multichannel receivers
Instrumentation
GENERAL DESCRIPTION
The AD8375 is a digitally controlled, variable gain, wide
bandwidth amplifier that provides precise gain control, high
IP3, and low noise figure. The excellent distortion performance
and high signal bandwidth make the AD8375 an excellent gain
control device for a variety of receiver applications.
Using an advanced high speed SiGe process and incorporating
proprietary distortion cancellation techniques, the AD8375
achieves 50 dBm output IP3 at 200 MHz.
The AD8375 provides a broad 24 dB gain range with 1 dB
resolution. The gain is adjusted through a 5-pin control interface
and can be driven using standard TTL levels. The open-collector
outputs provide a flexible interface, allowing the overall signal
gain to be set by the loading impedance. Thus, the signal
voltage gain is directly proportional to the load.
The AD8375 is powered on by applying the appropriate logic
level to the PWUP pin. The quiescent current of the AD8375 is
typically 130 mA. When powered down, the AD8375 consumes
less than 5 mA and offers excellent input-to-output isolation.
Ultralow Distortion IF VGA
AD8375
FUNCTIONAL BLOCK DIAGRAM
VPOS
COMM
VCOM
VIN+
VIN–
AD8375
α POST-AMP
REGISTERS
AND
GAIN DECODER
PWUP
OUT+
OUT+
OUT–
OUT–
A4 A3 A2 A1 A0
Figure 1.
Fabricated on an Analog Devices, Inc., high speed SiGe process,
the AD8375 is supplied in a compact, thermally enhanced,
4 mm × 4 mm, 24-lead LFCSP package and operates over the
temperature range of −40°C to +85°C.
–40 65
–50 60
–60 55
OIP3
–70 50
–80
–90
–100
HD2
HD3
45
40
35
–110
40
60
30
80 100 120 140 160 180 200
FREQUENCY (MHz)
Figure 2. Harmonic Distortion and Output IP3 vs. Frequency
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor for anyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD8375
Data Sheet
Parameter
Conditions
Min Typ
POWER INTERFACE
Supply Voltage
4.5 5.0
VPOS and Output Quiescent Current Thermal connection made to exposed paddle under device 120 125
vs. Temperature
−40°C ≤ TA ≤ +85°C
Power-Down Current
PWUP low
2.5
vs. Temperature
−40°C ≤TA ≤ +85°C
POWER-UP/GAIN CONTROL
Pin A0 to Pin A4, Pin PWUP
VIH
Minimum voltage for a logic high
1.6
VIL Maximum voltage for a logic low
Logic Input Bias Current
900
Max Unit
5.5 V
130 mA
150 mA
mA
3 mA
V
0.8 V
nA
Table 2. Gain Code vs. Voltage Gain Look-Up Table
5-Bit Binary Gain Code
Voltage Gain (dB)
00000
+20
00001
+19
00010
+18
00011
+17
00100
+16
00101
+15
00110
+14
00111
+13
01000
+12
01001
+11
01010
+10
01011
+9
01100
+8
5-Bit Binary Gain Code
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
>11000
Voltage Gain (dB)
+7
+6
+5
+4
+3
+2
+1
0
−1
−2
−3
−4
−4
Rev. A | Page 4 of 24
5 Page 
AD8375
2
1
CH1 500mV Ω CH2 500mV Ω M10.0ns 10.0GS/s IT 10.0ps/pt
A CH1 960mV
Figure 22. Gain Step Time Domain Response
2
1
CH1 500mV Ω CH2 500mV Ω M20.0ns 10.0GS/s IT 20.0ps/pt
A CH1 960mV
Figure 23. ENBL Time Domain Response
REF1 POSITION
–420mV/DIV
REF1 SCALE
0pF 2V
10pF EACH SIDE
INPUT
RRR431
REF1 2.0V 2.5ns
M2.5ns 20.0GS/s IT 10.0ps/pt
A CH4 28.0mV
Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB
Data Sheet
REF3 POSITION
–600mV/DIV
REF3 SCALE
0pF 500mV
10pF EACH SIDE
INPUT
RR13
REF3 500mV 2.5ns
M2.5ns 20.0GS/s IT 10.0ps/pt
A CH4 28.0mV
Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB
2
REF1
OUTPUT
INPUT
REF1 POSITION
–1.02/DIV
REF1 SCALE
50mV
RISE (C2) 1.384ns
FALL(C2) 1.39ns
CH2 500mV M2.5ns 20Gsps
REF1 50.0mV
IT 2.5ps/pt
A CH2
Figure 26. Large Signal Pulse Response
–610mV
0
–5
–10
–15
–20
–25
–30
10
100
FREQUENCY (MHz)
Figure 27. S11 vs. Frequency
180
120
60
0
–60
–120
–180
1000
Rev. A | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AD8375.PDF ] | |
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