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PDF AGM1064B Data sheet ( Hoja de datos )
| Número de pieza | AGM1064B | |
| Descripción | SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY | |
| Fabricantes | AZ Displays | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AGM1064B (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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AZ DISPLAYS, INC.
COMPLETE LCD SOLUTIONS
SPECIFICATIONS FOR
LIQUID CRYSTAL DISPLAY
www.DataSheet4U.com
PART NUMBER:
REVISED:
AGM1064B Series
MAY 14, 2003
1 page  
16 D1
17 D2
18 D3
When the serial interface is selected (P/S=“L”), then D7
serves as the serial data input terminal (SI) and D6 serves as
the serial clock input terminal (SCL). At this time, D0 to D5 are
set to high impedance.
When the chip select is inactive, D0 to D7 are set to high
impedance.
19 D4
20 D5
21 D6SCL
22 D7SI
23 DUTY0
Select the LCD driver duty
DUTY1 DUTY1
00
LCD driver duty
1/33
24 DUTY1
I
01
10
1/49
1/55
11
1/69
2.4 - 3.5V power supply input. These pads must be connected
25 VDD Supply each other.
26
VDD2
Supply
This is the power supply for the step-up voltage circuit for the
LCD. These pads must be connected each other.
27 VSS Supply Ground output for pad option.
28 VOUT
O DC/DC voltage converter output
29 NC
30 CAP3+
NC
O Capacitor 3+ pad for internal DC/DC voltage converter.
31 CAP1-
32 CAP1+
33 CAP2+
O Capacitor 1- pad for internal DC/DC voltage converter.
O Capacitor 1+ pad for internal DC/DC voltage converter.
O Capacitor 2+ pad for internal DC/DC voltage converter.
34 CAP2-
35 VEXT
O Capacitor 2- pad for internal DC/DC voltage converter.
This is the external input reference voltage (VREF) for the
internal voltage regulator. It is valid only when external VREF
I is used. VEXT must be ≥ 2.4V and ≤ VDD2. When using
internal VREF, this pad must be NC.
Page 4
5 Page 
3. Serial Interface Timing
Symbol
TSCYC
TSHW
TSLW
TSAS
TSAH
TSDS
TSDH
TCSS
TCSH
Parameter
Serial clock cycle
Serial clock H pulse
width
Serial clock L pulse
width
Address setup time
Address hold time
Data setup time
Data hold time
Chip select setup time
Chip select hold time
Min
250
100
100
150
150
100
100
150
150
TYP
-
-
MAX
-
-
--
--
--
--
--
--
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
*1. The input signal rise time and fall time (tr, tf) is specified at 15ns or less.
*2. All timing is specified using 20% and 80% of VDD as the standard.
Condition
SCL
SCL
SCL
D/I
D/I
SDI
SDI
CS1, CS2
CS1, CS2
Page 5
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet AGM1064B.PDF ] | |
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