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PDF AD7942 Data sheet ( Hoja de datos )
| Número de pieza | AD7942 | |
| Descripción | PulSAR ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7942 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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Preliminary Technical Data
14-Bit, 250 kSPS PulSAR™
ADC in MSOP/QFN
AD7942
FEATURES
APPLICATION DIAGRAM
14-bit resolution with no missing codes
0.5 TO 5V 2.5V to 5V
Throughput: 250 kSPS
INL: ±0.4 LSB typ, ±1 LSB max (±0.0061 % of FSR)
S/(N + D): 85 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Pseudo-differential analog input range
0 V to VREF with VREF up to VDD
No pipeline delay
0 TO VREF
REF VDD VIO
SDI
IN+
AD7942 SCK
IN– SDO
GND
CNV
1.8 TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
Single-supply 5V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Figure 1.
Serial interface SPI®/QSPI™/µWire/DSP compatible
Daisy chain multiple ADCs and BUSY indicator
Power dissipation
GENERAL DESCRIPTION
1.15 mW @ 2.5 V/100 kSPS, 3.3 mW @ 5 V/100 kSPS,
The AD7942 is a 14-bit, charge redistribution successive
1.15 µW @ 2.5 V/100 SPS
Stand-by current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
Pin-for-pin compatible with the 16-Bit AD7685
approximation, analog-to-digital converter (ADC) that operates
from a single 5V power supply, VDD. It contains a low power,
high speed, 14-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
www.DataSheet4U.comaperture delay track-and-hold circuit. On the CNV rising edge,
it samples an analog input IN+ between 0 V to REF with respect
to a ground sense IN−. The reference voltage, REF, is applied
externally and can be set up to the supply voltage.
Medical instruments
Its power scales linearly with throughput.
Process control
The SPI compatible serial interface also features the ability,
Table 1. MSOP, QFN (LFCSP)/SOT-23 14 and16-Bit ADC
Type
100 kSPS 250 kSPS 500 kSPS
16-Bit True
Differential
AD7684
AD7687
AD7688
using the SDI input, to daisy chain several ADCs on a single 3-
wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate
supply VIO.
16-Bit Pseudo
Differential/Unipolar
16-Bit Unipolar
AD7683
AD7680
AD7685
AD7694
AD7686
The AD7942 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
14-Bit Pseudo
Differential/Unipolar
AD7942 AD7946
14-Bit Unipolar
AD7940
Rev Pr B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
AD7942
TIMING SPECIFICATIONS
−40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 4. VDD = 4.5 V to 5.5 V1
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time between Conversions
CNV Pulse Width ( CS Mode )
SCK Period ( CS Mode )
SCK Period ( Chain Mode )
VIO above 4.5 V
VIO above 3 V
VIO above 2.7 V
VIO above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO above 4.5 V
VIO above 3 V
VIO above 2.7 V
VIO above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO above 4.5 V
VIO above 2.7 V
VIO above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with BUSY indicator)
VIO above 4.5 V
VIO above 2.3 V
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min Typ Max Unit
0.5 2.2 µs
1.8 µs
4 µs
10 ns
15 ns
19 ns
20 ns
21 ns
22 ns
7 ns
7 ns
5 ns
14 ns
15 ns
16 ns
17 ns
15 ns
18 ns
22 ns
25 ns
15 ns
0 ns
5 ns
5 ns
5 ns
4 ns
15 ns
26 ns
1 See Error! Reference source not found. and Error! Reference source not found. for load conditions.
Rev Pr B | Page 5 of 28
5 Page 
Preliminary Technical Data
AD7942
Figure 11. SNR vs. Temperature
Figure 14. SNR and THD vs. Input Level
Figure 12. THD vs. Frequency
Figure 15. Operating Currents vs. Supply
Figure 13. THD, SFDR vs. Temperature
Figure 16. Power-Down Currents vs. Temperature
Rev Pr B | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD7942.PDF ] | |
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