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NSTB1002DXV5T5G fiches techniques PDF

ON Semiconductor - (NSTB1002DXV5T1G / NSTB1002DXV5T5G) Dual Common Base-Collector Bias Resistor Transistors

Numéro de référence NSTB1002DXV5T5G
Description (NSTB1002DXV5T1G / NSTB1002DXV5T5G) Dual Common Base-Collector Bias Resistor Transistors
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NSTB1002DXV5T5G fiche technique
NSTB1002DXV5T1G,
NSTB1002DXV5T5G
Preferred Devices
Dual Common
Base−Collector Bias
Resistor Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSTB1002DXV5T1G
series, two complementary devices are housed in the SOT−553
package which is ideal for low power surface mount applications
where board space is at a premium.
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Available in 8 mm, 7 inch Tape and Reel
These are Pb−Free Devices
www.DataSheet4U.com
MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1
and Q2, − minus sign for Q1 (PNP) omitted)
Value
Rating
Symbol Q1 Q2 Unit
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
VCBO
VCEO
IC
−40
−40
−200
50
50
100
Vdc
Vdc
mAdc
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Symbol
Max
Unit
Total Device Dissipation
TA = 25°C PD 357 (Note 1) mW
Derate above 25°C
2.9 (Note 1) mW/°C
Thermal Resistance −
Junction-to-Ambient
RqJA 350 (Note 1) °C/W
Characteristic
(Both Junctions Heated)
Symbol
Max
Unit
Total Device Dissipation
TA = 25°C PD 500 (Note 1) mW
Derate above 25°C
4.0 (Note 1) mW/°C
Thermal Resistance −
Junction-to-Ambient
RqJA 250 (Note 1) °C/W
Junction and Storage Temperature
TJ, Tstg −55 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 @ Minimum Pad
http://onsemi.com
32
R1 R2
1
Q1
4
Q2
R1
5
5
1
SOT−553
CASE 463B
MARKING DIAGRAM
5
U9 MG
G
1
U9 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping
NSTB1002DXV5T1G SOT−553 4 mm pitch
(Pb−Free) 4000/Tape & Reel
NSTB1002DXV5T5G SOT−553 2 mm pitch
(Pb−Free) 8000/Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 0
1
Publication Order Number:
NSTB1002DXV5/D

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