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ON Semiconductor - (NSBA114EDXV6T5 Series) Dual Bias Resistor Transistors

Numéro de référence NSBA115EDXV6T1
Description (NSBA114EDXV6T5 Series) Dual Bias Resistor Transistors
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NSBA115EDXV6T1 fiche technique
NSBA114EDXV6T1,
NSBA114EDXV6T5 SERIES
Preferred Devices
Dual Bias Resistor
Transistors
PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSBA114EDXV6T1
series, two BRT devices are housed in the SOT−563 package which is
ideal for low−power surface mount applications where board space is
at a premium.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
These are Pb−Free Devices
MAXIMUM RATINGS
www.DataSheet4U.com
(TA = 25°C unless otherwise noted, common for Q1 and Q2)
Rating
Symbol Value
Unit
Collector-Base Voltage
VCBO −50 Vdc
Collector-Emitter Voltage
VCEO
−50
Vdc
Collector Current
IC
−100
mAdc
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Symbol Max
Unit
Total Device Dissipation @ TA = 25°C PD 357 mW
Derate above 25°C (Note 1)
2.9 mW/°C
Thermal Resistance, Junction-to-Ambient RqJA
(Note 1)
350 °C/W
Characteristic
(Both Junctions Heated)
Total Device Dissipation @ TA = 25°C
Derate above 25°C (Note 1)
Symbol
PD
Max
500
4.0
Unit
mW
mW/°C
Thermal Resistance, Junction-to-Ambient RqJA
(Note 1)
250 °C/W
Junction and Storage Temperature
Range
TJ, Tstg
−55 to
+150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−4 @ Minimum Pad
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 6
1
http://onsemi.com
(3) (2) (1)
R1 R2
Q1
R2 R1
Q2
(4) (5)
(6)
SOT−563
CASE 463A
PLASTIC
1 STYLE 1
MARKING DIAGRAM
xx M G
G
xx = Device Code
(Refer to page 2)
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping
NSBA1xxxDXV6T1 SOT−563* 4000/Tape & Reel
NSBA1xxxDXV6T1G SOT−563* 4000/Tape & Reel
NSBA1xxxDXV6T5 SOT−563* 8000/Tape & Reel
NSBA1xxxDXV6T5G SOT−563* 8000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
**This package is inherently Pb−Free.
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
NSBA114EDXV6/D

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