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ON Semiconductor - HDPlus Dual N-Channel Self-protected Field Effect Transistors

Numéro de référence NIMD6302R2
Description HDPlus Dual N-Channel Self-protected Field Effect Transistors
Fabricant ON Semiconductor 
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NIMD6302R2 fiche technique
NIMD6302R2
HDPlus Dual N−Channel
Self−protected Field Effect
Transistors with 1:200
Current Mirror FET
HDPlus devices are an advanced HDTMOSseries of power
MOSFET which utilize ON’s latest MOSFET technology process to
achieve the lowest possible on−resistance per silicon area while
incorporating smart features. They are capable of withstanding high
energy in the avalanche and commutation modes. The avalanche
energy is specified to eliminate guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
This HDPlus device features an integrated Gate−to−Source clamp
for ESD protection. Also, this device features a mirror FET for current
monitoring.
±3.5% Current Mirror Accuracy in Linear Region
±15% Current Mirror Accuracy in Low Current Saturation Region
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Current Sense FET
ESD Protected on the Main and the Mirror FET
ABSOLUTE MAXIMUM RATINGS
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Stresses beyond those listed may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated in this specification is not
implied. Exposure to absolute maximum rated conditions for extended peri-
ods may affect device reliability.
MAIN MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.0 MW)
Gate−to−Source Voltage
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C (Note 3)
− Pulsed (tpv10 ms)
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
Thermal Resistance
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Single Pulse Drain−to−Source Avalanche
Energy (Note 3)
(VDD = 25 Vdc, VGS = 10 Vdc,
VDS = 20 Vdc, IL = 15 Apk, L = 10 mH, RG =
25 W)
VDSS
VDGR
VGS
ID
ID
IDM
PD
PD
RqJA
RqJA
EAS
30
30
"16
Vdc
Vdc
Vdc
6.5 Adc
4.4 Adc
33 Apk
1.3 W
1.67
°C/W
96
75
250 mJ
1. Mounted onto min pad board.
2. Mounted onto 1pad board.
3. Switching characteristics are independent of operating junction tempera-
tures.
http://onsemi.com
5.0 AMPERES
30 VOLTS
RDS(on) = 50 mW
ISOLATED DUAL PACKAGING
Drain1
Drain2
Gate1
Mirror Main
FET
Gate2
Mirror Main
FET
Mirror1 Source1
Mirror2 Source2
SOIC−8
CASE 751
STYLE 19
MARKING DIAGRAM
Source 1
Gate 1
Source 2
Gate 2
1
2
3
4
8
Mirror 1
7
Drain 1
6
Mirror 2
5
Drain 2
(Top View)
N6302
A
Y
WW
= Specific Device Code
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
NIMD6302R2
SOIC−8 2500/Tape & Reel
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 4
1
Publication Order Number:
NIMD6302R2/D

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