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PDF ADC14V155 Data sheet ( Hoja de datos )
| Número de pieza | ADC14V155 | |
| Descripción | 14-Bit Bandwidth A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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April 2007
ADC14V155
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with
LVDS Outputs
General Description
Features
The ADC14V155 is a high-performance CMOS analog-to-
digital converter with LVDS outputs. It is capable of converting
analog input signals into 14-Bit digital words at rates up to 155
Mega Samples Per Second (MSPS). Data leaves the chip in
a DDR (Dual Data rate) format; this allows both edges of the
output clock to be utilized while achieving a smaller package
size. This converter uses a differential, pipelined architecture
with digital error correction and an on-chip sample-and-hold
circuit to minimize power consumption and the external com-
ponent count, while providing excellent dynamic perfor-
mance. A unique sample-and-hold stage yields a full-power
■ 1.1 GHz Full Power Bandwidth
■ Internal sample-and-hold circuit
■ Low power consumption
■ Internal precision 1.0V reference
■ Single-ended or Differential clock modes
■ Clock Duty Cycle Stabilizer
■ Dual +3.3V and +1.8V supply operation (+/- 10%)
■ Power-down and Sleep modes
■ Offset binary or 2's complement output data format
bandwidth of 1.1 GHz. The ADC14V155 operates from dual
+3.3V and +1.8V power supplies and consumes 951 mW of
power at 155 MSPS.
■ LVDS outputs
■ 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)
The separate +1.8V supply for the digital output interface al- Key Specifications
lows lower power operation with reduced noise. A power-
down feature reduces the power consumption to 15 mW while ■ Resolution
still allowing fast wake-up time to full operation. In addition ■ Conversion Rate
there is a sleep feature which consumes 50 mW of power and ■ SNR (fIN = 70 MHz)
has a faster wake-up time.
■ SFDR (fIN = 70 MHz)
The differential
swing equal to
inputs
2 times
provide a full
the reference
scale differential
voltage. A stable
i1n.wp0wuVwt.DataSh■■eet4EFU.ucNolmOl PBo(wfIeNr=B7a0ndMwHidzt)h
internal voltage reference is provided, or the ADC14V155 can ■ Power Consumption
be operated with an external reference.
14 Bits
155 MSPS
71.7 dBFS (typ)
86.9 dBFS (typ)
11.5 bits (typ)
1.1 GHz (typ)
951 mW (typ)
Clock mode (differential versus single-ended) and output data
format (offset binary versus 2's complement) are pin-se-
lectable. A duty cycle stabilizer maintains performance over
a wide range of input clock duty cycles.
Applications
■ High IF Sampling Receivers
■ Wireless Base Station Receivers
It is available in a 48-lead LLP package and operates over the ■ Power Amplifier Linearization
industrial temperature range of −40°C to +85°C.
■ Multi-carrier, Multi-mode Receivers
■ Test and Measurement Equipment
■ Communications Instrumentation
■ Radar Systems
Block Diagram
© 2007 National Semiconductor Corporation 300052
30005202
www.national.com
1 page  
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VA, VD)
Supply Voltage (VDR)
|VA–VD|
−0.3V to 4.2V
−0.3V to 2.35V
≤ 100 mV
Voltage on Any Input Pin
(Not to exceed 4.2V)
−0.3V to (VA +0.3V)
Voltage on Any Output Pin
(Not to exceed 2.35V)
-0.3V to (VDR +0.2V)
Input Current at Any Pin other
than Supply Pins (Note 3)
±5 mA
Package Input Current (Note 3)
±50 mA
Max Junction Temp (TJ)
Thermal Resistance (θJA)
Package Dissipation at TA = 25°
C (Note 4)
+150°C
24°C/W
5.2W
ESD Rating
Human Body Model (Note 5)
2000 V
Machine Model (Note 5)
200 V
Charge Device Model
1000 V
Storage Temperature
−65°C to +150°C
Soldering process must comply with National
Semiconductor's Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.
(Note 6)
Operating Ratings (Notes 1, 2)
Operating Temperature
Supply Voltage (VA, VD)
Output Driver Supply (VDR)
CLK
Clock Duty Cycle
Analog Input Pins
VCM
|AGND-DGND|
−40°C ≤ TA ≤ +85°C
+3.0V to +3.6V
+1.6V to +2.0V
−0.05V to (VA + 0.05V)
30/70 %
0V to 2.6V
1.4V to 1.6V
≤100mV
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5 www.national.com
5 Page 
Timing Diagram
Transfer Characteristic
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Output Timing
30005220
30005210
FIGURE 1. Transfer Characteristic (Offset Binary Format)
11
www.national.com
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ADC14V155.PDF ] | |
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