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PDF NCP5201 Data sheet ( Hoja de datos )
| Número de pieza | NCP5201 | |
| Descripción | Dual Output DDR Power Controller | |
| Fabricantes | ON Semiconductor | |
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NCP5201
Dual Output
DDR Power Controller
The NCP5201 Dual DDR Power Controller is specifically
designed as a total power solution for a high current DDR memory
system. This IC combines the efficiency of a PWM controller for the
VDDQ supply with the simplicity of a linear regulator for the VTT
memory termination voltage. The secondary regulator (VTT) is
designed to automatically track at half the primary regulator voltage
(VDDQ). An internal power good voltage monitor tracks both
VDDQ and VTT outputs and notifies the user in the event of a fault
on either output. Protective features include soft−start circuitry and
undervoltage monitoring of VCC and VSTBY. The IC is packaged in
a 5 × 6 QFN−18.
Features
• Incorporates VDDQ, VTT Regulators
• Internal Switching Standby Regulator for VDDQ
• All External Power MOSFETs Are N−Channel
• Adjustable VDDQ
• VTT Tracks VDDQ/2
• Fixed Switching Frequency of 250 kHz for VDDQ in Normal Mode
• Doubled Switching Frequency (500 kHz) for Standby Mode
• Soft−Start Protection for VDDQ
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• Undervoltage Monitor
• Short−Circuit Protection for Both VDDQ and VTT Outputs
• Housed in a space saving 5 × 6 QFN−18
• Pb−Free Packages are Available*
Typical Applications
• DDR Termination Voltage
• Active Termination Busses (SSTL−2, SSTL−3)
http://onsemi.com
MARKING
DIAGRAM
1
18−LEAD QFN, 5 x 6 mm
MN SUFFIX
CASE 505
1
NCP5201
AWLYYWW G
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
FBDDQ
FBVTT
PGND
VSTBY
VTT
VTT
OCDDQ
VDDQ
NC
1
2
3
4
5
6
7
8
9
18 SS
17 COMP
16 VCC
15 TGDDQ
14 BGDDQ
13 SDDQ
12 AGND
11 S3_EN
10 PWRGD
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 11
1
NOTE: Pin 19 is the thermal pad on the bottom of
the device.
ORDERING INFORMATION
Device
Package
Shipping†
NCP5201MN
18−Lead QFN 61 Units / Rail
NCP5201MNG
18−Lead QFN 61 Units / Rail
(Pb−Free)
NCP5201MNR2 18−Lead QFN 2500/Tape & Reel
NCP5201MNR2G 18−Lead QFN 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NCP5201/D
1 page  
NCP5201
S3_EN
VCC
VSTBY
PWRGD
SS
Voltage and
Current Reference
VREF
VREFGD
TSD
12 V
12 V−
UVLO
+
−
12 VGD
VREF
VSTBY
5 VST−
UVLO
+ VSTGD
−
VREF
Control
Logic
S0
S3
INREGVTT
INREGDDQ
ILIM
+
−
VDDQ
PWM
Logic
Thermal
Shutdown
IREF
12 V
PGND
VSTBY
S0
PGND S3
OSC
S0
S3
PWM−
COMP
+−
VREF
AMP +
A
−
PGND
12 V
PGND
OCDDQ
TGDDQ
VSTBY
SDDQ
BGDDQ
COMP
FBDDQ
R
R
R
R
GND
SC2PWR
+
−
S3
S0
INREGDDQ
INREGVTT
SC2GND
+
−
VTT
Regulation
Control
VSTBY
PGND
VSTBY
PGND
VDDQ
VTT
PGND
FBVTT
AGND
Figure 2. Internal Block Diagram
PGND
http://onsemi.com
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet NCP5201.PDF ] | |
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