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PDF NBSG53A Data sheet ( Hoja de datos )
| Número de pieza | NBSG53A | |
| Descripción | 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider | |
| Fabricantes | ON Semiconductor | |
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NBSG53A
2.5V/3.3V SiGe Selectable
Differential Clock and Data
D Flip−Flop/Clock Divider
with Reset and OLS*
The NBSG53A is a multi−function differential D flip−flop (DFF) or
fixed divide by two (DIV/2) clock generator. This is a part of the
GigaComm™ family of high performance Silicon Germanium
products. A strappable control pin is provided to select between the
two functions. The device is housed in a low profile 4x4 mm 16−pin
Flip−Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.
The NBSG53A is a device with data, clock, OLS*, reset, and select
inputs. Differential inputs incorporate internal 50 W termination
resistors and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to
program the peak−to−peak output amplitude between 0 and 800 mV
in five discrete steps. The RESET and SELECT inputs are
single−ended and can be driven with either LVECL or
LVCMOS/LVTTL input levels.
Data is transferred to the outputs on the positive edge of the clock.
The differential clock inputs of the NBSG53A allow the device to also
be used as a negative edge triggered device.
Features
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• Maximum Input Clock Frequency (DFF) > 8 GHz Typical
(See Figures 4, 6, 8, 10, and 11)
• Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
(See Figures 5, 7, 9, 10, and 11)
• 210 ps Typical Propagation Delay (OLS = FLOAT)
• 45 ps Typical Rise and Fall Times (OLS = FLOAT)
• DIV/2 Mode (Active with Select Low)
• DFF Mode (Active with Select High)
• Selectable Swing PECL Output with Operating Range: VCC = 2.375 V
to 3.465 V with VEE = 0 V
• Selectable Swing NECL Output with NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
• Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV
Peak−to−Peak Output)
• 50 W Internal Input Termination Resistors on all Differential Inputs
• Pb−Free Packages are Available
*Output Level Select
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MARKING
DIAGRAM**
FCBGA−16
BA SUFFIX
CASE 489
1
QFN−16
MN SUFFIX
CASE 485G
SG
53A
LYW
ÇÇÇÇ16
1
SG
53A
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 8
1
Publication Order Number:
NBSG53A/D
1 page  
NBSG53A
Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 8)
−40°C
25°C
70°C(BGA)/85°C(QFN)**
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
IEE
VOH
VOL
VOUTPP
VIH
Negative Power Supply Current
33 45
Output HIGH Voltage (Note 9)
1460 1510
Output LOW Voltage (Note 9)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
555
1235
775
1455
1005
705
1295
895
1505
1095
Output Voltage Amplitude
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
670
125
510
0
325
800
215
615
5
415
Input HIGH Voltage (Single−Ended)
VEE + VCC −
(Notes 11 and 13)
CLK, CLK, D, D 1275 1000*
57
1560
855
1385
1015
1585
1215
VCC
33 45 57
1490 1540 1590
595
1270
810
1490
1040
745
1330
930
1540
1130
895
1420
1050
1620
1250
660 795
120 210
505 610
00
320 410
VEE + VCC −
1275 1000*
VCC
33
1515
625
1295
840
1510
1065
655
120
500
0
320
VEE +
1275
45
1565
775
1355
960
1560
1155
790
210
605
5
410
VCC−
1000*
57
1615
925
1445
1080
1640
1275
VCC
mA
mV
mV
mV
mV
VIL Input LOW Voltage (Single−Ended)
VEE VCC− VIH− VEE VCC− VIH− VEE VCC− VIH− mV
(Notes 12 and 13)
CLK, CLK, D, D
1400* 150
1400* 150
1400* 150
VIH
VIL
VTHR
Input High Voltage (Single−Ended)
R, SEL 1290
Input Low Voltage (Single−Ended)
R, SEL VEE
Input Threshold Voltage (Single−Ended) VEE+
(Note 13)
1125
VCC 1355
890
VCC−
75
VEE
VEE+
1125
VCC 1415
955
VCC−
75
VEE
VEE+
1125
VCC
1015
VCC−
75
mV
mV
mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
1.2
2.5 1.2
2.5 1.2
2.5 V
RTIN
IIH
Internal Input Termination Resistor
Input HIGH Current (@VIH)
R, SEL
CLK, CLK, D, D
45
50 55 45
35 100
5 50
50 55 45
35 100
5 50
50 55 W
35 100 mA
5 50
IIL
Input LOW Current (@VIL)
R, SEL
CLK, CLK, D, D
20 100
5 50
20 100
5 50
20 100 mA
5 50
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V.
9. All outputs loaded with 50 W to VCC − 2.0 V.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
11. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
12. VIL always w VEE. |VIL − VTHR| < 2600 mV.
13. VTHR is the voltage applied to one input when running in single−ended mode.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
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5
5 Page 
NBSG53A
900
OLS = VCC
800
9
8
700 OLS = VCC − 0.8 V, OLS = FLOAT
600
7
6
500 *OLS = VEE
5
400 4
300 OLS = VCC − 0.4 V
3
200 2
100 1
RMS JITTER
00
0 1 2 3 4 5 6 7 8 9 10 11 12
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for DFF Mode (VCC − VEE = 3.3 V @ 255C; Repetitive 1010 Input Data Pattern)
900
OLS = VCC
800
700 OLS = VCC − 0.8 V, OLS = FLOAT
600
500 *OLS = VEE
400
300 OLS = VCC − 0.4 V
200
100
0
0 1 2 3 4 5 6 7 8 9 10 11 12
INPUT FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for DIV/2 Mode (VCC − VEE = 3.3 V @ 255C)
*When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
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11
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet NBSG53A.PDF ] | |
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