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PDF 80C154 Data sheet ( Hoja de datos )
| Número de pieza | 80C154 | |
| Descripción | CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller | |
| Fabricantes | TEMIC Semiconductors | |
| Logotipo |  |
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80C154/83C154
CMOS 0 to 36 MHz Single Chip 8–bit Microcontroller
Description
TEMIC’s 80C154 and 83C154 are high performance
CMOS single chip µC. The 83C154 retains all the
features of the 80C52 with extended ROM capacity (16
K bytes), 256 bytes of RAM, 32 I/O lines, a 6-source
2-level interrupts, a full duplex serial port, an on-chip
oscillator and clock circuits, three 16 bit timers with extra
features : 32 bit timer and watchdog functions. Timer 0
and 1 can be configured by program to implement a 32 bit
timer. The watchdog function can be activated either with
timer 0 or timer 1 or both together (32 bit timer).
In addition, the 83C154 has 2 software-selectable modes
of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM is saved, and the timers, the serial port and the
interrupt system continue to function. In the power down
mode the RAM is saved and the timers, serial port and
interrupt continue to function when driven by external
clocks. In addition as for the TEMIC 80C51/80C52, the
stop clock mode is also available.
The 80C154 is identical to the 83C154 except that it has
no on-chip ROM. TEMIC’s 80C154 and 83C154 are
manufactured using SCMOS process which allows them
to run from 0 up to 36 MHz with Vcc = 5 V.
D 80C154 : ROMless version of the 83C154µ
D 80C154/83C154-12 : 0 to 12 MHz
D 80C154/83C154-16 : 0 to 16 MHz
D 80C154/83C154-20 : 0 to 20 MHz
D 80C154/83C154-25 : 0 to 25 MHz
D 80C154/83C154-30 : 0 to 30 MHz
D 80C154/83C154-36 : 0 to 36 MHz
D 80C154/83C154-L16 : Low power version
VCC : 2.7-5.5 V Freq : 0-16 MHz
For other speed and temperature range availability please consult your
sales office.
Features
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D Power control modes
D 256 bytes of RAM
D 16 Kbytes of ROM (83C154)
D 32 Programmable I/O lines (programmable impedance)
D Three 16 bit timer/counters (including watchdog and 32 bit
timer)
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8µ CMOS process
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range : commercial, industrial, automotive,
military
Optional
D Secret ROM : Encryption
D Secret TAG : Identification number
MATRA MHS
Rev.F (14 Jan. 97)
1
1 page  
80C154/83C154
ALE
Address Latch Enable output for latching the low byte of
the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of
1/6 the oscillator frequency except during an external
data memory access at which time one ALE pulse is
skipped. ALE can sink or source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
PSEN
Program Store Enable output is the read strobe to external
Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory.
(However, when executing out of external Program
Memory, two activations of PSEN are skipped during
each access to external Data Memory). PSEN is not
activated during fetches from internal Program Memory.
PSEN can sink/source 8 LS TTL inputs. It can drive
CMOS inputs without an external pullup.
XTAL1
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator,
and input to the internal clock generator. This pin should
be floated when an external oscillator is used.
EA
When EA is held high, the CPU executed out of internal
Program Memory (unless the Program Counter exceeds
3FFFH). When EA is held low, the CPU executes only out
of external Program Memory. EA must not be floated.
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Idle and Power Down Operation
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. The interrupt, serial port, and timer
blocks continue to function only with external clock
(INT0, INT1, T0, T1).
Figure 3. Idle and Power Down Hardware.
Idle Mode operation allows the interrupt, serial port, and
timer blocks to continue to function with internal or
external clocks, while the clock to CPU is gated off. The
special modes are activated by software via the Special
Function Register, PCON. Its hardware address is 87H.
PCON is not bit addressable.
MATRA MHS
Rev.F (14 Jan. 97)
5
5 Page 
32 Bit Counter
Figure 13 illustrates the 32 bit COUNTER mode.
Figure 12. 32 Bit Counter Configuration.
80C154/83C154
D In this mode, T32 = 0 and C/T0 = 1. Before it can
make an increment, the 83C154µ must detect two
transitions on its T0 input. As shown in figure 14,
Figure 13. Counter Incrementation Condition.
input T0 is sampled on each S5P2 state of every
machine cycle or, in other words, every OSC ÷ 12.
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D The counter will only evolve if a level 1 is detected
during state S5P2 of cycle Ci and if a level 0 is
detected during state S5P2 of cycle Ci + n.
D Consequently, the minimal period of signal fEXT
admissible by the counter must be greater than or
equal to two machine cycles. The following formula
should be used to calculate the operating frequency.
f
+
fEXT
65536ć(T0,
Ă
T1)
fEXT
t
OSC
24
Figure 14. The Different Watchdog Configurations.
Watchdog Mode
D WDT = 1 enables access to this mode. As shown in
figure 15, all the modes of TIMERS 0 and 1, of which
the overflows act on TF1 (TF1 = 1), activate the
WATCHDOG Mode.
MATRA MHS
Rev.F (14 Jan. 97)
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet 80C154.PDF ] | |
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