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PDF WM8195 Data sheet ( Hoja de datos )
| Número de pieza | WM8195 | |
| Descripción | 14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser | |
| Fabricantes | Wolfson Microelectronics | |
| Logotipo |  |
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WM8195
14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser
DESCRIPTION
FEATURES
The WM8195 is a 14-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12MSPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset Adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 14-bit
analogue-to-digital converter. The digital output data is
available in 14-bit parallel or 8, 7 or 4-bit wide multiplexed
format, with no missing codes.
• 14-bit ADC
• No missing codes guaranteed
• 12MSPS conversion rate
• Low power – 210mW typical
• 5V single supply or 5V/3.3V dual supply operation
• Single or 3 channel operation
• Correlated double sampling
• Programmable gain (8-bit resolution)
• Programmable offset adjust (8-bit resolution)
• Programmable clamp voltage
• 14-bit parallel or 8, 7 or 4-bit wide multiplexed data output
formats
• Internally generated voltage references
• 48-lead TQFP package
An internal 4-bit DAC is supplied for internal reference level
• Serial or parallel control interface
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
APPLICATIONS
signals. Alternatively an external reference level may be
applied. ADC references are generated internally, ensuring
optimum performance from the device.
• Flatbed and sheetfeed scanners
• USB compatible scanners
• Multi-function peripherals
Using an analogue supply voltage of 5V and a digital
• High-performance CCD sensor interface
interface supply of either 5V or 3.3V, the WM8195 typically
only consumes 210mW when operating from a single 5V
www.DataSheet4U.com
supply and less than 20µA when in power down mode.
BLOCK DIAGRAM
VRLC/VBIAS
CL
RINP
RLC
GINP
RLC
VSMP MCLK
AVDD1-2
DVDD1-3
RS VS
M
U
X
TIMING CONTROL
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WM8195
CDS
RM
GU
X
B
8
OFFSET
DAC
VREF/BIAS
+ PGA
RM
GU
X
B
I/P SIGNAL
8 POLARITY
ADJUST
CDS
+ PGA
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
VRT VRX VRB
+
M
+U
X
14-
BIT
ADC
DATA
I/O
PORT
BINP
RLC
RLC
DAC 4
CDS
+ PGA
+
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
INTERFACE
OEB
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
OP[8]
OP[9]
OP[10]
OP[11]
OP[12]
OP[13]/SDO
SEN/STB
SCK/RNW
SDI/DNA
RLC/ACYC
NRESET
AGND1-6
DGND1-5
WOLFSON MICROELECTRONICS plc
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Production Data July 2005 Rev 4.1
Copyright 2005 Wolfson Microelectronics plc.
1 page  
Production Data
WM8195
PIN NAME
TYPE
DESCRIPTION
31 OP[7]
Digital I/O
See pins 21 to 23 for details.
32 OP[8]
Digital I/O
33 OP[9]
Digital I/O
34 OP[10]
Digital I/O
35 DVDD3
Supply
Digital I/O supply (3.3V/5V).
36 DGND4
Supply
Digital ground (0V).
37 OP[11]
Digital I/O
See pins 21 to 23 for details.
38 OP[12]
39 OP[13]/SDO
Digital I/O
Digital I/O
If the device has been configured to use the serial interface, pin OP[13]/SDO may
be used to output register read-back data when OEB = 0 and SEN has been
pulsed high.
See Serial Interface sections in Device Description for further details.
40 DGND5
Supply
Digital ground (0V).
41 NC
No connection.
42
NRESET
Digital input Reset input, active low. This signal forces a reset of all internal registers and selects
whether the serial or parallel control interface is used. See pin SEN/STB.
43 AVDD1
Supply
Analogue supply (5V).
44 AVDD2
Supply
Analogue supply (5V).
45 AGND5
Supply
Analogue ground (0V).
46 AGND6
Supply
Analogue ground (0V).
47
VRB
Analogue output Lower reference voltage. This pin must be capacitively decoupled to AGND.
48
VRT
Analogue output Lower reference voltage. This pin must be capacitively decoupled to AGND.
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PD Rev 4.1 July 2005
5
5 Page 
Production Data
WM8195
SERIAL INTERFACE
SCK
SDI
SEN
SDO
tSPER
tSSU
tSH
tSCKL tSCKH
tSCE
ADC DATA
tSEW tSEC
tSERD
tSCRD
t SCRDZ
MSB
LSB
REGISTER DATA
ADC
DATA
Figure 5 Serial Interface Timing
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SCK period
SYMBOL
tSPER
TEST CONDITIONS
SCK high
tSCKH
SCK low
tSCKL
SDI set-up time
tSSU
SDI hold time
tSH
SCK to SEN set-up time
tSCE
SEN to SCK set-up time
tSEC
SEN pulse width
tSEW
SEN low to SDO = Register data
tSERD
SCK low to SDO = Register data
tSCRD
SCK low to SDO = ADC data
tSCADC
Note: Parameters are measured at 50% of the rising/falling edge.
MIN
41.6
18.8
18.8
6
6
12
12
25
TYP
MAX
30
30
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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PD Rev 4.1 July 2005
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WM8195.PDF ] | |
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