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PDF NB6N14S Data sheet ( Hoja de datos )
| Número de pieza | NB6N14S | |
| Descripción | Differential Input to LVDS Fanout Buffer/Translator | |
| Fabricantes | ON Semiconductor | |
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NB6N14S
3.3 V 1:4 AnyLevelt
Differential Input to LVDS
Fanout Buffer/Translator
The NB6N14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevelt differential input signals: LVPECL, CML or
LVDS. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N14S has a wide input common mode range from
GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6N14S is ideal for
translating a variety of differential or single−ended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N14S is offered in a small 3 mm x 3 mm 16−QFN
package. Application notes, models, and support documentation are
available at www.onsemi.com.
The NB6N14S is a member of the ECLinPS MAXt family of high
performance products.
Features
• Maximum Input Clock Frequency > 2.0 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• 1 ps Maximum RMS Clock Jitter
www.DataSheet4U.com
• Typically 10 ps Data Dependent Jitter
• 380 ps Typical Propagation Delay
• 120 ps Typical Rise and Fall Times
• VREF_AC Reference Output
• TIA/EIA − 644 Compliant
• Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
• These are Pb−Free Devices
Device DDJ = 10 ps
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6N
14S
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
IN
VT
/IN
50 W
50 W
EN
(LVTTL/CMOS)
VREF_AC
DQ
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 3
1
Publication Order Number:
NB6N14S/D
1 page  
NB6N14S
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 12)
−40°C
Symbol
Characteristic
Min Typ Max
finMax
Maximum Input Clock Frequency
2.0
VOUTPP
Output Voltage Amplitude (@ VINPPmin) fin ≤ 1.0 GHz
(Figure 4)
fin= 1.5 GHz
fin= 2.0 GHz
220
200
170
350
300
270
fDATA
Maximum Operating Data Rate
1.5 2.5
tPLH,
tPHL
Differential Input to Differential Output
Propagation Delay
300 450 600
ts Setup Time
th Hold Time
300 60
500 70
tSKEW
Within Device Skew (Note 17)
Device−to−Device Skew (Note 16)
5 20
30 200
25°C
Min Typ Max
2.0
220 350
200 300
170 270
1.5 2.5
300 450 600
300 60
500 70
5 20
30 200
85°C
Min Typ Max
2.0
220 350
200 300
170 270
1.5 2.5
300 450 600
300 60
500 70
5 20
30 200
Unit
GHz
mV
Gb/s
ps
ps
tJITTER
VINPP
RMS Random Clock Jitter (Note 14) fin = 1.0 GHz
fin = 1.5 GHz
Deterministic Jitter (Note 15) fDATA = 622 Mb/s
fDATA = 1.5 Gb/s
fDATA = 2.488 Gb/s
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 13)
100
0.5
0.5
10
10
10
VCC− 100
GND
0.5
0.5
10
10
10
VCC− 100
GND
0.5 ps
0.5
10
10
10
VCC− mV
GND
tr Output Rise/Fall Times @ 250 MHz
tf (20% − 80%)
Q, Q 60 120 190 60 120 190 60 120 190 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W. Input
edge rates 150 ps (20%−80%). See Figure 13.
13. Input voltage swing is a single−ended measurement operating in differential mode.
14. RMS jitter with 50% Duty Cycle clock signal at 750 MHz.
15. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
16. Skew is measured between outputs under identical transition @ 250 MHz.
17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
400
350
300
250 −40°C
200 85°C
25°C
150
100
50
0
0 0.5 1 1.5 2 2.5 3
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
http://onsemi.com
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