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PDF NTHD4401P Data sheet ( Hoja de datos )

Número de pieza NTHD4401P
Descripción Power MOSFET ( Transistor )
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



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NTHD4401P
Power MOSFET
−20 V, −3.0 A, Dual P−Channel, ChipFETt
Features
Low RDS(on) and Fast Switching Speed in a ChipFET Package
Leadless ChipFET Package 40% Smaller Footprint than TSOP−6
ChipFET Package with Excellent Thermal Capabilities where Heat
Transfer is Required
Pb−Free Package is Available
Applications
Charge Control in Battery Chargers
Optimized for Battery and Load Management Applications in
Portable Equipment
MP3 Players, Cell Phones, Digital Cameras, PDAs
Buck and Boost DC−DC Converters
http://onsemi.com
V(BR)DSS
−20 V
RDS(on) TYP
130 mW @ −4.5 V
200 mW @ −2.5 V
ID MAX
−3.0 A
S1 S2
G1 G2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Pulsed Drain Current
Steady
State
TA = 25°C
TA = 85°C
t v 5 s TA = 25°C
Steady
State
TA = 25°C
TA = 85°C
t v 5 s TA = 25°C
tp = 10 ms
Operating Junction and Storage Temperature
VDSS
VGS
ID
PD
IDM
TJ, Tstg
−20 V
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−2.1 A
−1.5
−3.0
1.1 W
0.6
2.1
−9.0 A
−55 to
150
°C
Source Current (Body Diode)
Lead Temperature for Soldering Purposes
(1/8from case for 10 s)
IS −2.5 A
TL 260 °C
THERMAL RESISTANCE RATINGS
Rating
Symbol Value Unit
Junction−to−Ambient − Steady State (Note 1) RqJA
110 °C/W
Junction−to−Ambient − t v 5 s
60
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 4
1
D1
P−Channel MOSFET
D2
P−Channel MOSFET
ChipFET
CASE 1206A
STYLE 2
PIN
CONNECTIONS
MARKING
DIAGRAM
D1 8
D1 7
D2 6
D2 5
1 S1
2 G1
3 S2
4 G2
1
2
3
4
8
7
6
5
C4 = Specific Device Code
M = Month Code
G = Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
NTHD4401PT1 ChipFET 3000/Tape & Reel
NTHD4401PT1G ChipFET 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTHD4401P/D

1 page




NTHD4401P pdf
1.0
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E−03
1.0E−02
NTHD4401P
Normalized to θJA at 10s.
Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.0154 F 0.0854 F
0.3074 F 1.7891 F
107.55 F Ambient
1.0E−01
1.0E+00
t, TIME (s)
Figure 12. Thermal Response
1.0E+01
1.0E+02
1.0E+03
0.457
0.018
2.032
0.08
SOLDERING FOOTPRINT*
0.635
0.025
0.635
0.025
2.032
0.08
1.092
0.043
0.178
0.007
0.66
0.026
0.711
0.028
ǒ ǓSCALE 20:1
mm
inches
Figure 13. Basic
0.457
0.018
0.66
0.026
0.254
0.010
SCALE 20:1
ǒ mm Ǔ
inches
Figure 14. Style 2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 13. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.
The minimum recommended pad pattern shown in
Figure 14 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
leadframe) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
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