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PDF M13L128168A Data sheet ( Hoja de datos )
| Número de pieza | M13L128168A | |
| Descripción | DDR SDRAM | |
| Fabricantes | EliteMT | |
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ESMT
Revision History
Revision 1.3
-Revise operation voltage. (page 5)
Revision 1.2
-Changed tWTR from 1 tCK to 2 tCK.
Revision 1.1
-Changed absolute max. voltage (VIN, VOUT ,VDD ,VDDQ) from 3.6V to 4.0V
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
VIN, VOUT
VDD
VDDQ
-0.5 ~ 4.0
-1.0 ~ 4.0
-0.5 ~ 4.0
V
V
V
-Changed operating VDD from 3.135V~3.6V to 3.135V~3.83V
-Updated DC current specification
Revision 1.0 (21 Oct. 2002)
-No “preliminary” on title.
-Added M13L128168A-3.6T Spec.
-Changed VDDQ from 2.5V ± 5% to 2.375V ~ 2.8V
Revision 0.4 (26 Sep. 2002)
-Changed VDD from 3.3V ± 5% to 3.135V ~ 3.6V
-Changed operating temperature from 70 °C to 65 °C
Revision 0.3 (11 Jul. 2002)
-Added DC Current Spec
www.DataSheet4U.com
Revision 0.2 (29 May. 2002)
-Independent of M13S128168A
Revision 0.1 (3 May. 2002)
-Original
M13L128168A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2003
Revision : 1.3
1/48
1 page  
ESMT
M13L128168A
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Storage temperature
Power dissipation
Short circuit current
VIN, VOUT
VDD
VDDQ
TSTG
PD
IOS
-0.5 ~ 3.6
-1.0 ~ 4.0
-0.5 ~ 4.0
-55 ~ +150
TBD
50
V
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 °C ~ 65 °C )
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Symbol
VDD
VDDQ
VREF
Vwww.DataSheet4U.comTT
VIH (DC)
VIL (DC)
VIN (DC)
Min
3.135
2.375
0.49*VDDQ
VREF - 0.04
VREF + 0.15
-0.3
-0.3
Max
3.6
2.8
0.51*VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
VDDQ + 0.3
Unit
V
V
V
V
V
V
V
Note
1
2
Input Differential Voltage, CLK and CLK inputs
VID (DC)
0.36
VDDQ + 0.6
V
Input leakage current
Output leakage current
Output High Current (Normal strength driver)
(VOUT = VTT+0.76)
Output Low Current (Normal strength driver)
(VOUT = VTT -0.76 )
Output High Current (Weak strength driver)
(VOUT = VTT+0.45)
Output Low Current (Weak strength driver)
(VOUT = VTT-0.45)
II -5
IOZ -5
IOH -15.2
IOL +15.2
IOH -9
IOL +9
5
5
µA 3
µA
mA
mA
mA
mA
Notes 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF .
3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2003
Revision : 1.3
5/48
5 Page 
ESMT
M13L128168A
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of
different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS setting
for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0 (The DDR
SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. One clock cycle is
requested to complete the write operation in the mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into
various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from
column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation.
Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
00
RFU
DLL TM
CAS Latency
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BT
Burst Length
A8 DLL Reset
0 No
1 Yes
A7 Mode
0 Normal
1 Test
A3 Burst Type
0 Sequential
1 Interleave
Burst Length
Mode Register
BA0 BA0
00
01
Operating Mode
MRS Cycle
EMRS Cycle
CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
Latency
Reserve
Reserve
2
3
Reserve
Reserve
Reserve
Reserve
Latency
A2 A1 A0
Sequential Interleave
0 0 0 Reserve Reserve
001
2
2
010
4
4
011
8
8
1 0 0 Reserve Reserve
1 0 1 Reserve Reserve
1 1 0 Reserve Reserve
1 1 1 Reserve Reserve
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2003
Revision : 1.3
11/48
11 Page | ||
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| PDF Descargar | [ Datasheet M13L128168A.PDF ] | |
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