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PDF ACS760ELF-20B Data sheet ( Hoja de datos )
| Número de pieza | ACS760ELF-20B | |
| Descripción | High-Side Hot-Swap Hall Effect Based Current Monitor | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Features and Benefits
Description
▪ Hall-effect current monitor—no external sense resistor required
▪ Analog output voltage (factory trimmed for gain and
offset) proportional to applied current
▪ External high-side FET gate drive
▪ 240V*A Power Fault Protection with user-programmable delay
▪ User programmable Overcurrent Fault Protection with
The ACS760 combines Allegro® Hall-effect current sense
technology with a hot-swap controller resulting in a more
efficient integrated controller for 12 V applications. By
eliminating the need for a shunt resistor, the I2R losses in the
power path are reduced.
programmable delay
When the ACS760 is externally enabled, and the voltage rail is
▪ 1.5 mΩ internal conductor resistance
above the internal UVLO threshold, the internal charge pump
▪ Short Circuit Protection isolates failed supply from
drives the gate of the external FET. When a fault is detected, the
output in < 2 μs
gate is disabled while simultaneously alerting the application
▪ Active low Fault indicator output signal
that a fault has occurred.
▪ External FET failure detection with active low S1 Short
failure indicator output signal
▪ User controlled soft start / hot-swap function
▪ Logic enable input pin
▪ 10.8 to 13.2 V, single-supply operation
▪ 2 kV ESD protection for all pins
The integrated protection in the ACS760 incorporates three
levels of fault protection, which includes a Power Fault with
user-programmable delay, a user-programmable Overcurrent
Fault threshold with programmable delay, and Short Circuit
protection, which disables the gate in less then 2 μs.
Package: 24 pin QSOP (suffix LF)
Additionally, in the event the external high-side FET fails
short, theACS760 detects the S1 Short failure and immediately
disables the gate and alerts the host system. Unlike the three
www.DataSheetp4Ur.cootmection faults, cycling the EN pin does not reset the S1 Short
failure. Power to the device must be cycled.
Approximate Scale
Typical Application
VS_IN
VS_RET
Backplane
IP
RV1
A
CIN
Enable
REN
CEN
VOUT
RSET
CG
COCD
COPD
1
IP+
24
IP–
2
IP+
23
IP–
3
IP+
22
IP–
4 21
IP+
5
ACS760
IP–
20
IP+ IP–
6
IP+
19
IP–
7
EN
18
GATE
8
VIOUT
17
GND
9
ISET
16
FB–
10
CG
15
FB+
11
OCDLY
14
S1SHORT
12
OPDLY
13
FAULT
S1
RG
RFB
C
A RV1 is required only for inductive loads.
B D1 should be a Schottky for inductive loads, to eliminate over-stress of the ACS760.
C FB– is tied to GND at the point of load.
CLOAD
VLOAD
D1
B
3.3 V
RS1
RFAULT
760ELF20B-DS, Rev. 2
1 page  
ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor
OPERATING CHARACTERISTICS valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted
Characteristic
Symbol
Test Conditions
GENERAL ELECTRICAL CHARACTERISTICS
Linear Sensing Range
IP Current flows from IP+ to IP- pins
Primary Conductor Resistance
RPRIMARY TA = 25°C
Supply Voltage
VCC Voltage applied to IP+ pins
Supply Current
ICC
Undervoltage Lockout (UVLO)
VUVLOH VCC rising and CG pin current source turns on, EN pin = high
VUVLOL VCC falling and CG pin current source turns off, EN pin = high
UVLO Delay to Chip Enable/ Disable
tUVLOE Enabling, measured from rising VCC > VUVLOH to VGATE > 1 V
tUVLOD Disabling, from falling VCC < VUVLOL to VGATE < 1 V
FB+ to FB– Input Resistance
RFB TA = 25°C
CURRENT SENSE PERFORMANCE CHARACTERISTICS
VIOUT Analog Output Propagation
Time
tPROP
TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND
= 100 pF
VIOUT Analog Output 10-90% Rise
Time
tr
TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND
= 100 pF
VIOUT Analog Signal Bandwidth1
f3dB
–3 dB, Ip = 10 A peak-to-peak, TA = 25°C, no external device
filter, capacitance from VIOUT to GND = 100 pF
VIOUT Analog Signal Sensitivity
Sens
TA = 25°C
Over full ambient operating temperature range
TA = 25°C
Over full ambient operating temperature range
VIOUT Analog Noise Level
VIOUT Analog Nonlinearity
VNOISE(PP) Mean peak-to-peak, TA = 25°C, 50 kHz external device filter
ELIN
Over full ambient operating temperature range and linear
sensing range
Zero Current Output Voltage
VIOUT(Q)
TA = 0 to 55°C
TA = 0 to 85°C
Output Voltage Saturation Limits2
VOL TA = 25°C
VOH TA = 25°C
VIOUT Total Error % of IP
ETOT
TA = 25°C, IP = 20 A
TA = 0 to 85°C, IP = 20 A
VIOUT DC Output Resistance
RVIOUT IVIOUT = 1 mA
CURRENT FAULT PERFORMANCE CHARACTERISTICS
Load Power Fault Threshold
240 V*A Fault Signal Delay
PF(th)
tPFH
TA = 25°C, measured from FAULT signal to VGATE < 1 V,
2.2 μF capacitance from OPDLY pin to GND, load step from
17 A to 23 A in 100 ns
tPFL
TA = 25°C, measured from FAULT signal to VGATE < 1 V,
OPDLY pin open, load step from 17 A to 23 A in 100 ns
240 V*A Fault Signal Delay Drift
∆tPF
Over full operating ambient temperature range, external
capacitor with ±5% tolerance
Internal –3 dB Filter Frequency for FB+
and FB– Pins
fFBFILT TA = 25°C
IP Fault Switchpoint Tolerance3
EPF
tIPFLmax
Percentage error of IPF
Measured from FAULT signal to VGATE < 1 V, OCDLY pin
open, load step from 17 A to 45 A in 100 ns
IPF Fault Signal Delay4
tIPFH
Measured from FAULT signal to VGATE < 1 V, 2.2 nF capaci-
tance from OCDLY pin to GND, load step from 17 A to 45 A
in 100 ns
Min.
0
–
–
–
–
7.1
–
–
–
–
–
–
–
63
–
5.275
–
–
0.38
0.37
–
–
–
–
–
222
–
–
–15
–
–15
–
–
Typ.
–
1.5
12
10
–
–
500
–
240
2
5
50
65
–
5.416
–
20
±0.5
–
0.4
0.25
3.6
±1.0
–
1
230
425
10
–
50
–
8
425
Max.
55
–
13.2
12
10.5
–
900
2
–
–
–
–
–
67
–
5.558
–
±2.0
0.42
0.43
–
–
–
±3.5
–
238
–
12
15
–
15
12
–
Units
A
mΩ
V
mA
V
V
μs
μs
kΩ
μs
μs
kHz
mV/A
mV/A
mV/G
mV/G
mV
%
V
V
V
V
%
%
Ω
W
ms
μs
%
kHz
%
μs
μs
Continued on the next page…
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5 Page 
ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor
S1 Short Fault Operation
The timing diagram in figure 4 shows the characteristic operation
of the ACS760 when the power consumed from the 12 V system
bus exceeds a 240 V*A or 240 W level. For the operation during a
240 V*A fault condition, refer to figure 1. That section describes
the operation of the ACS760 until the time t240VA_F. Figure 4
depicts a 240 V*A fault, but continues on to demonstrate the abil-
ity of the ACS760 to detect damage and improper operation of
the external MOSFET in an S1 short circuit event.
At t240VA_F, the FAULT signal transitions to the low state and the
ACS760 pulls down the voltage on the GATE pin. During normal
operation, when the GATE pin is at 0 V, the current through the
S1 MOSFET (and therefore through the ACS760) equals approxi-
mately 0 A. However, in the case depicted in figure 4, current
through the S1 MOSFET flows even though the GATE pin is
pulled low. If a FAULT has occurred and more than 2.1 A flow
through the ACS760, then the S1SHORT signal transitions to the
low state. When the S1SHORT signal is low, that indicates to the
system that the ACS760 cannot turn off the external MOSFET
(for example, when a short circuit exists between the source and
the drain of the MOSFET). In the case depicted, the system shuts
down the 12 V power supply after the S1SHORT signal transi-
tions to the low state.
Note that, in some cases, the GATE of the S1 MOSFET may be
shorted to the source or drain of the MOSFET. In this case the
ACS760 may not be able to pull down the gate of the S1 MOS-
FET. However, in this case the ACS760 will still register an S1
Short even if the gate potential is equal to or greater than 12 V.
If the ACS760 is disabled (EN pin in the low state) and greater
than 2.1 A flows through the ACS760, then the device will reg-
ister an S1 Short condition and the S1SHORT pin will transition
to the low state. The voltage on the GATE pin is not used as a
determining factor when sensing an S1 Short condition.
The S1SHORT signal will not reset to a high state until power
to the device is cycled. Toggling the EN pin does not reset the
latched S1 Short state.
Determining the Root Cause of an ACS760 Fault Event
The following truth table provides system debugging information
in the event of a fault event during use of the ACS760. Note that
for all of the fault conditions listed, it is possible to monitor the
voltages of various ACS760 output pins and determine the cause
of the ACS760 FAULT event.
Figure 4. Timing Diagram for S1 Short
Fault Condition Truth Table
Pin Logic State
FAULT Pin
OPDLY Pin
Low High
Low Don’t Care
Low Low
OCDLY Pin
Low
High
Low
Probable Root Cause
240 V*A system power level, PF(th), exceeded
IP Fault Current Threshold, IPF, exceeded
Short Circuit Fault Threshold, ISC, exceeded
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
11 Page | ||
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| PDF Descargar | [ Datasheet ACS760ELF-20B.PDF ] | |
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