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PDF CAT1024 Data sheet ( Hoja de datos )
| Número de pieza | CAT1024 | |
| Descripción | (CAT1024 / CAT1025) Supervisory Circuits | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CAT1024 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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CAT1024, CAT1025
Supervisory Circuits with I2C Serial 2k-bit
CMOS EEPROM and Manual Reset
FEATURES
DESCRIPTION
Precision Power Supply Voltage Monitor
— 5V, 3.3V and 3V systems
— Five threshold voltage options
Active High or Low Reset
— Valid reset guaranteed at VCC = 1V
The CAT1024 and CAT1025 are complete memory
and supervisory solutions for microcontroller-based
systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together in low power CMOS techno–
logy. Memory interface is via a 400kHz I2C bus.
400kHz I2C Bus
2.7V to 5.5V Operation
Low power CMOS technology
16-Byte Page Write Buffer
Built-in inadvertent write protection
— WP pin (CAT1025)
The CAT1025 provides a precision VCC sense circuit
and two open drain outputs: one (RESET) drives high
and the other (R¯¯E¯S¯E¯T¯) drives low whenever VCC falls
below the reset threshold voltage. The CAT1025 also
has a Write Protect input (WP). Write operations are
disabled if WP is connected to a logic high.
1,000,000 Program/Erase cycles
Manual Reset Input
100 year data retention
The CAT1024 also provides a precision VCC sense
circuit, but has only a R¯¯E¯S¯E¯T¯ output and does not
have a Write Protect input.
Industrial and extended temperature ranges Thewww.DataSheet4U.com power supply monitor and reset circuit protect
Green packages available with NiPdAu Lead
finished
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200 ms after the supply
voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to
microcontrollers and other ICs is simple. In addition,
the R¯¯E¯S¯E¯T¯ pin or a separate input, ¯M¯R¯, can be used
For Ordering Information details, see page 19.
as an input for push-button manual reset capability.
The CAT1024/25 memory features a 16-byte page. In
addition, hardware data protection is provided by a
VCC sense circuit that prevents writes to memory
whenever VCC falls below the reset threshold or until
VCC reaches the reset threshold during power up.
Available packages include an 8-pin DIP and a
surface mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN
and 8-pin MSOP packages. The TDFN package thick-
ness is 0.8mm maximum. TDFN footprint is 3x3mm.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 3008 Rev. N
1 page  
CAT1024, CAT1025
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol
COUT(1)
CIN(1)
Test
Output Capacitance
Input Capacitance
Test Conditions
VOUT = 0V
VIN = 0V
Max
8
6
Units
pF
pF
AC CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol Parameter
Min Max Units
fSCL Clock Frequency
tSP Input Filter Spike Suppression (SDA, SCL)
400 kHz
100 ns
tLOW Clock Low Period
1.3 µs
tHIGH
tR(1)
tF(1)
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
0.6
300
300
µs
ns
ns
tHD; STA
tSU; STA
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
0.6 µs
0.6 µs
tHD; DAT Data Input Hold Time
0 ns
tSU; DAT Data Input Setup Time
100 ns
tSU; STO Stop Condition Setup Time
0.6 µs
tAA SCL Low to Data Out Valid
900 ns
tDH Data Out Hold Time
50 ns
tBUF(1) Time the Bus must be Free Before a New Transmission Can Start
1.3
µs
tWC(3) Write Cycle Time (Byte or Page)
5 ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 3008 Rev. N
5 Page 
CAT1024, CAT1025
Page Write
The CAT1024/25 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of
terminating after the initial byte is transmitted, the
Master is allowed to send up to 15 additional bytes.
After each byte has been transmitted, the CAT1024/25
will respond with an acknowledge and internally
increment the lower order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 16 bytes before
sending the STOP condition, the address counter
‘wraps around,’ and previously transmitted data will be
overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1024/25 in a single write cycle.
Figure 8. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
SLAVE
ADDRESS
BYTE
ADDRESS
A
C
K
A
C
K
DATA
S
T
O
P
P
A
C
K
Figure 9: Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
SLAVE
ADDRESS
BYTE
ADDRESS (n)
AA
CC
KK
DATA n
DATA n+1
AA
CC
KK
S
T
DATA n+15
O
P
P
A
C
K
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 3008 Rev. N
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CAT1024.PDF ] | |
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