48LC2M32B2 Datasheet PDF - MICRON
| Part Number | 48LC2M32B2 | |
| Description | MT48LC2M32B2 | |
| Manufacturers | MICRON | |
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SYNCHRONOUS
DRAM
64Mb: x32
SDRAM
MT48LC2M32B2 - 512K x 32 x 4 banks
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/sdramds
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3
OPTIONS
• Configuration
2 Meg x 32 (512K x 32 x 4 banks)
• Plastic Package - OCPL1
86-pin TSOP (400 mil)
• Timing (Cycle Time)
5ns (200 MHz)
5.5ns (183 MHz)
6ns (166 MHz)
7ns (143 MHz)
• Operating Temperature Range
Commercial (0° to +70°C)
Extended (-40°C to +85°C)
NOTE: 1. Off-center parting line
2. Available on -7
MARKING
2 M 3 2 B 2www.DataSheet4U.com
TG
-5
-55
-6
-7
None
IT2
Part Number Example:
MT48LC2M32B2TG-7
PIN ASSIGNMENT (TOP VIEW)
86-PIN TSOP
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86 VSS
85 DQ15
84 VSSQ
83 DQ14
82 DQ13
81 VDDQ
80 DQ12
79 DQ11
78 VSSQ
77 DQ10
76 DQ9
75 VDDQ
74 DQ8
73 NC
72 VSS
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 VSS
57 NC
56 DQ31
55 VDDQ
54 DQ30
53 DQ29
52 VSSQ
51 DQ28
50 DQ27
49 VDDQ
48 DQ26
47 DQ25
46 VSSQ
45 DQ24
44 VSS
KEY TIMING PARAMETERS
SPEED
GRADE
-5
-55
-6
-7
CLOCK ACCESS TIME
FREQUENCY CL = 3*
200 MHz
183 MHz
166 MHz
143 MHz
4.5ns
5ns
5.5ns
5.5ns
SETUP
TIME
1.5ns
1.5ns
1.5ns
2ns
*CL = CAS (READ) latency
HOLD
TIME
1ns
1ns
1ns
1ns
Note: The # symbol indicates signal is active LOW.
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
2 Meg x 32
512K x 32 x 4 banks
4K
2K (A0-A10)
4 (BA0, BA1)
256 (A0-A7)
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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64Mb: x32
SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL TYPE
DESCRIPTION
68 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
67 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous
except after the device enters power-down and self refresh modes, where
CKE becomes asynchronous until after exiting the same mode. The input
buffers, including CLK, are disabled during power-down and self refresh
modes, providing low standby power. CKE may be tied HIGH.
20 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH.
CS# provides for external bank selection on systems with multiple banks.
CS# is considered part of the command code.
17, 18, 19
WE#, CAS#, Input Command Inputs: WE# , CAS#, and RAS# (along with CS#) define the
RAS#
command being entered.
16, 71, 28, 59
DQM0-
DQM3
Input
Input/Output Mask: DQM is sampled HIGH and is an input mask signal
for write accesses and an output enable signal for read accesses. Input data
is masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) during a READ cycle. DQM0 corresponds to DQ0-
DQ7; DwQwwM.Da1taSchoeert4rUe.csopmonds to DQ8-DQ15; DQM2 corresponds to DQ16-DQ23;
and DQM3 corresponds to DQ24-DQ31. DQM0-DQM3 are considered same
state when referenced as DQM.
22, 23
BA0,BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
25-27, 60-66, 24
A0-A10
Input
Address Inputs: A0-A10 are sampled during the ACTIVE command (row-
address A0-A10) and READ/WRITE command (column-address A0-A7 with A10
defining auto precharge) to select one location out of the memory array in
the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
2, 4, 5, 7, 8, 10, 11, 13,
74, 76, 77, 79, 80, 82, 83,
85, 31, 33, 34, 36, 37, 39,
40, 42, 45, 47, 48, 50, 51,
53, 54, 56
DQ0-DQ31 Input/ Data I/Os: Data bus.
Output
14, 21, 30, 57, 69, 70, 73
NC
– No Connect: These pins should be left unconnected. Pin 70 is reserved
for SSTL reference voltage supply.
3, 9, 35, 41, 49, 55, 75, 81 VDDQ Supply DQ Power Supply: Isolated on the die for improved noise immunity.
6, 12, 32, 38, 46, 52, 78, 84 VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
1, 15, 29, 43
VDD Supply Power Supply: +3.3V ±0.3V. (See note 27 on page 35.)
44, 58, 72, 86
VSS Supply Ground.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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