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PDF CAT24C208 Data sheet ( Hoja de datos )
| Número de pieza | CAT24C208 | |
| Descripción | 8-Kb Dual Port Serial EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT24C208
8-Kb Dual Port Serial EEPROM
FEATURES
I Supports Standard and Fast I2C protocol*
I 2.5V to 5.5V operation
I 16-byte page write buffer
I Schmitt triggers and noise protection filters
on I2C bus input
I Low power CMOS technology
I 1,000,000 program/erase cycles
I 100 year data retention
I Industrial temperature range
I RoHS-compliant 8-lead SOIC package
DESCRIPTION
The CAT24C208 is an 8-Kbit Dual Port Serial CMOS
EEPROM internally organized as 4 segments of 256
bytes each. The CAT24C208 features a 16-byte page
write buffer and can be accessed from either of two
separate I2C compatible ports, DSP (SDA, SCL) and
DDC (SDA, SCL).
Arbitration between the two interface ports is automatic
and allows the appearance of individual access to the
memory from each interface.
For Ordering Information details, see page 12.
www.DataSheet4U.com
BLOCK DIAGRAM
DSP VCC
DSP SCL
DSP SDA
DISPLAY
CONTROL
LOGIC
D
E
C
O
D
E
R
S
ARBITRATION
LOGIC
1K X 8
MEMORY
ARRAY
DDC VCC
D
E
C
O
D
DDC
CONTROL
DDC SCL
E
LOGIC
DDC SDA
R
S
VSS
CONFIGURATION
REGISTER
EDID SEL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1044, Rev. F
1 page  
CAT24C208
FUNCTIONAL DESCRIPTION
The CAT24C208 has a total memory space of 1K bytes
which is accessible from either of two I2C interface
ports, (DSP_SDA and DSP_SCL) or (DDC_SDA and
DDC_SCL), and with the use of segment pointer at
address 60h. On power up and after any instruction, the
segment pointer will be in segment 00h for DSP and in
segment 00h of the bank selected by the configuration
register for DDC.
The entire memory appears as contiguous memory
space from the perspective of the display interface
(DSP_SDA and DSP_SCL), see Table 2, and Figures
11 to Figure 18 for a complete description of the DSP
Interface.
A configuration register at addresses 62/63h is used to
configure the operation and memory map of the device
as seen from the DDC interface, (DDC_SDA and
DDC_SCL).
Read and write operations can be performed on any
location within the memory space from the display DSP
interface regardless of the state of the EDID SEL pin or
the activity on the DDC interface. From the DDC
interface, the memory space appears as two 512 byte
banks of memory, with 2 segments each 00h and 01h in
the upper and lower bank, see Table 1.
Each bank of memory can be used to store an E-EDID
data structure. However, only one bank can be read
through the DDC port at a time. The active bank of
memory (that is, the bank that appears at address A0h
on the DDC port) is controlled through the configuration
register at 62/63h and the EDID_SEL pin.
No write operations are possible from the DDC interface
unless the DDC Write Enable bit is set (WE = 1) in the
device configuration register at device address 62h.
The device automatically arbitrates between the two
interfaces to allow the appearance of individual access
to the memory from each interface.
In a typical E-EDID application the EDID_SEL pin is
usually connected to the “Analog Cable Detect” pin of a
VESA M1 compliant, dual-mode (analog and digital)
display. In this manner, the E-EDID appearing at ad-
dress A0h on the DDC port will be either the analog or
digital E-EDID, depending on the state of the “Analog
Cable Detect” pin (pin C3 of the M1-DA connector). See
Figure 1.
Figure 1.
TO HOST
CONTROLLER
28 DDC +5V
47.5K
10K
C3
27 DDC CLK
26 DDC DATA
FUSE, RESISTOR
OR OTHER CURRENT
LIMITING DEVICE
REQUIRED IN ALL M1 DISPLAYS
+5V DC
(SUPPLIED
BY DISPLAY)
81
72
E-EDID
6 EEPROM 3
54
I2C TO PROJECTOR/MONITOR
DISPLAY CONTROLLER
8 HPD
2A MAX
RELAY CONTACTS SHOWN IN
DE-ENERGIZED POSITION
Table 1: DDC Interface
MEMORY ARRAY
Upper
Bank
Lower
Bank
01
00
01
00
Segment 1
256 Bytes
Segment 0
256 Bytes
Segment 1
256 Bytes
Segment 0
256 Bytes
00
00
Address by
Configuration
Segment
Register
Pointer
No
Segment
Pointer
(see Figure 19)
Table 2: DSP Interface
MEMORY ARRAY
11 Segment 3
256 Bytes
10 Segment 2
256 Bytes
01 Segment 1
256 Bytes
00 Segment 0 00
256 Bytes
Segment Pointer
No Segment Pointer
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1044, Rev. F
5 Page 
PACKAGING INFORMATION
8-Lead 150 MIL SOIC (W)
E1
E
CAT24C208
D
A
e
b
A1
SYMBOL
A1
A
b
C
D
E
E1
e
h
L
θ1
MIN
0.10
1.35
0.33
0.19
4.80
5.80
3.80
0.25
0.40
0°
NOM
1.27 BSC
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
0.50
1.27
8°
h x 45
θ1
L
C
8-LEAD_SOIC.eps
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MS-012.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc No. 1044, Rev. F
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CAT24C208.PDF ] | |
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