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PDF VP5513 Data sheet ( Hoja de datos )
| Número de pieza | VP5513 | |
| Descripción | (VP5313 / VP5513) NTSC/PAL Digital Video Encoder | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de VP5513 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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VP5313/VP5513
PIN DESCRIPTIONS
Pin Name
PD0-7
PXCK
Pin No.
2-4,
38-42
44
SA
SCL
SDA
FC0-2
REFSQ
SCSYNC
PALID
COMPSYNC
CLAMP
18
23
24
12-14
9
8
7
6
5
TTXREQ
TTXDATA
HSYNC
VSYNC
RESET
VREF
RREF
17
19
15
16
22
33
34
DACCOMP
CVBS1
25
32
BLUE/CVBS2
GREEN/Y
RED/C
VDD
AVDD
GND
AGND
31
27
26
1, 11, 20
37,28,30
10,21,43
36,29,35
Description
8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit. These pins are
internally pulled low.
27MHz Pixel Clock input. The VP5313/VP5513 internally divides PXCK by two to provide the
pixel clock.
Slave address select.
Standard I2C bus serial clock input.
Standard I2C bus serial data input/output.
Field Counter output in master sync mode.
Reference square wave input used only during Genlock mode.
Subcarrier sync input, (synchronises phase quadrant in 4xfsc genlock mode), see fig 6.
PAL IDENT input, controls swinging colour burst phase in PAL genlock mode.
Composite sync pulse output. This is an active low output signal.
The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of
the BURST pulse, (lines 10-263 and 273-525 for NTSC; lines 6-310 and 319-623 for PAL-
B,D,G,I,N(Argentina)).
Teletext Data Request output, requests next line of teletext data.
Teletext Data input.
Horizontal Sync, output in master mode, input in slave mode
Vertical Sync, output in master mode, input in slave mode
Master reset. This is an asynchronous, active low, input signal and must be asserted for a
minimum 200ns in order to reset the VP5313/VP5513.
Voltage reference output. This output is nominally 1·0V and should be decoupled with a
100nF capacitor to GND.
DAC full scale current control. A resistor connected between this pin and GND sets the
magnitude of the video output current. An internal loop amplifier controls a reference current
flowing through this resistor so that the voltage across it is equal to the Vref voltage. This
reference current has a weighting equal to 20.8 LSB’s.
DAC compensation. A 100nF ceramic capacitor must be connected to AVDD.
Composite video output. These are high impedance current source outputs. A DC path to
GND must exist from each of these pins.
Blue or composite DAC output. Output type as CVBS1.
Green or luminance DAC output. Output type as CVBS1.
Red or chrominance DAC output. Output type as CVBS1.
Positive supply input. All VDD pins must be connected.
Analog positive supply input. All AVDD pins must be connected.
Negative supply input. All GND pins must be connected.
Analog negative supply input. All AGND pins must be connected.
4
5 Page 
default (power up) the TRS slave mode is selected. All internal
timing signals are derived from the input clock, (PXCK) this
must be derived from a crystal controlled oscillator. Input pixel
data is latched on the rising edge of the PXCK clock.
The video timing generator produces the internal blanking and
burst gate pulses, together with the composite sync output
signal.
H&V slave mode is enabled by setting the SYNCM1-0 bits
in the MODE register to 01. In this mode the position of the
video syncs is derived from the HS and VS inputs. These HS
and VS pins are automatically configured as inputs.
Video Timing - Master sync mode
When SYNCM1-0 of the MODE register are 10, the
VP5313/VP5513 operates in a MASTER sync mode, all
REC656 timing reference codes are ignored with VS, HS and
FC0-2 outputs providing synchronisation signals to an
external (MPEG) device. The PXCK signal is, however, still
used to generate all internal clocks. In master mode the
direction setting of bits 4 - 0 of the IICEXCTL register are
ignored.
VS is the start of the field sync datum in the middle of the
equalisation pulses. HS is the line sync which is used by the
preceding MPEG2 decoder to define when to output digital
video data to the VP5313/VP5513. The position of the falling
edge of HS relative to the first data Cb0, can be programmed
in HSOFFM-L registers, see figure 5.
Genlock using REFSQ input
The VP5313/VP5513 can be Genlocked to another video
source by setting GENLKEN high (in GCR register) and
feeding a phase coherent sub carrier frequency signal into
REFSQ. Under normal circumstances, REFSQ will be the
same frequency as the sub carrier; however if FSC4SEL is set
high (in GCR register), a 4 x sub carrier frequency signal may
be input to REFSQ. In this case, the Genlock circuit can be
reset to the required phase of REFSQ, by supplying a pulse
to SCSYNC. The frequency of SCSYNC can be at the sub
carrier frequency, once per line or once per field could be
adequate, depending on the application. When GENLKEN is
set high, the direction setting of bit 5 of the IICEXCTL register
is ignored.
PALID input
When using PAL and Genlock mode; the VP5313/VP5513
requires a PAL phase identification signal, to define the
correct phase on every line. This is supplied to PALID input,
High = -135° and low = +135°. The signal is asynchronous,
and should by changed before the sub carrier burst signal.
PALID input is enabled by setting PALIDEN high (in GCR
register). When PALIDEN is set high, the direction setting of
bit 7 of the IICEXCTL register is ignored.
Line 21 coding
Two bytes of data are coded on the line 21 of each field,
see figure 8. In the NTSC Closed Caption service, the default
state is to code on line 21 of field one only. An additional
service can also be provided using line 21 (284) of the second
field. The data is coded as NRZ with odd parity, after a clock
run-in and framing code. The clock run-in frequency =
0.5034965MHz which is related to the nominal line period, D
= H / 32.
D = 63.55555556 / 32µs
VP5313/VP5513
Two data bytes per field are loaded via I2C bus registers
CCREG1-4. Each field can be independently enabled by
programming the enable bits in the control register (CC_CTL).
The data is cleared to zero in the Closed Caption shift
registers after it has been encoded by the VP5313/VP5513.
Two status bit are provided (in CC_CTL), which are set high
when data is written to the registers and set low when the data
has been encoded on the Luma signal. The data is cleared to
zero in the Closed Caption shift registers after it has been
encoded by the VP5313/VP5513. The next data bytes must
be written to the registers when the status bit goes high,
otherwise the Closed Caption data output will contain Null
characters. If a transmission slot is missed (ie. no data
received) the encoder will send Null characters. Null
characters are invisible to a closed caption reciever. The MSB
(bit 7) is the parity bit and is automatically added by the
encoder.
Teletext
The Teletext function within the VP5313/VP5513 co-
ordinates the insertion of teletext serial data into the
luminance data stream and subsequently the composite video
data stream.
The serial data is filtered prior to insertion to minimise the
high frequency components and to reduce the jitter inherent in
the digital data stream.
The lines in which teletext data are inserted are individually
programmable for both even and odd fields. The insertion of
teletext data will only be enabled if the format of the composite
video is configured to be PAL-B,G,H,I,N and the teletext
enable bit TTXEN is asserted.
For test purposes, the teletext function incorporates
control logic to generate a serial clock cracker pattern in place
of the normal teletext data. This test pattern is enabled when
the TTX_PAT bit is asserted. There is no row coding used so
it will not display on a TV.
The VP5313/VP5513 teletext interface comprises of a
teletext request output, TTX_REQ, and a serial data input,
TTX_DATA.
To ensure that the composite video timing requirements
are satisfied, the serial data must be received at a specific
point in time during lines containing teletext data. The teletext
request output, TTX_REQ, will be asserted to indicate when
data must be applied to TTX_DATA, which must be generated
synchronous to the rising edges of PXCK. The TTX_REQ may
be advanced in multiples of PXCK, to compensate for the
latency within the source device, by writing to the TTXDD
register.
The serial teletext data which is applied to the TTX_DATA
input must obey the sequence defined below.
The teletext bit rate is defined to be 6.9375 MHz, which
equates to 444 times the PAL line frequency (15.625 kHz). It
is clear that for a 27 MHz system clock, a constant bit period
cannot be achieved.
10
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet VP5513.PDF ] | |
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