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PDF MC74LVX573 Data sheet ( Hoja de datos )
| Número de pieza | MC74LVX573 | |
| Descripción | Octal D-Type Latch | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74LVX573
Octal D−Type Latch
with 3−State Outputs
With 5 V−Tolerant Inputs
The MC74LVX573 is an advanced high speed CMOS octal latch
with 3−state outputs. The inputs tolerate voltages up to 7.0 V, allowing
the interface of 5.0 V systems to 3.0 V systems.
This 8−bit D−type latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
Features
• High Speed: tPD = 6.4 ns (Typ) at VCC = 3.3 V
• Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Low Noise: VOLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model > 2000 V;
Machine Model > 200 V
• Pb−Free Packages are Available*
www.DataSheet4U.com
http://onsemi.com
MARKING
DIAGRAMS
20
SOIC−20
DW SUFFIX
CASE 751D
LVX573
AWLYYWW
1
TSSOP−20
DT SUFFIX
CASE 948E
LVX
573
ALYW
VCC O0 O1 O2 O3 O4 O5 O6 O7 LE
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
Figure 1. 20−Lead Pinout (Top View)
SOEIAJ−20
M SUFFIX
CASE 967
LVX573
AWLYWW
A = Assembly Location
WL, L = Wafer Lot
Y, YY = Year
W, WW = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
March, 2005 − Rev. 3
1
Publication Order Number:
MC74LVX573/D
1 page  
D 50%
tPLH
O 50% VCC
Figure 3.
OE
O
O
50%
tPZL tPLZ
50% VCC
tPZH tPHZ
50% VCC
Figure 5.
MC74LVX573
SWITCHING WAVEFORMS
VCC
GND
tPHL
tw
LE 50%
tPLH
tPHL
O 50% VCC
Figure 4.
VCC
GND
HIGH
IMPEDANCE
VOL +0.3 V
VOL −0.3 V
HIGH
IMPEDANCE
VALID
D 50%
tsu th
LE 50%
Figure 6.
VCC
GND
VCC
GND
VCC
GND
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 7. Propagation Delay Test Circuit
*Includes all probe and jig capacitance
Figure 8. 3−State Test Circuit
http://onsemi.com
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74LVX573.PDF ] | |
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