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PDF LM1851 Data sheet ( Hoja de datos )
| Número de pieza | LM1851 | |
| Descripción | GROUND FAULT INTERRUPTER | |
| Fabricantes | Unisonic Technologies | |
| Logotipo |  |
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UTC LM1851
LINEAR INTEGRATED CIRCUIT
GROUND FAULT INTERRUPTER
DESCRIPTION
The UTC LM1851 is designed to provide ground fault
protection for AC power outlets in consumer and industrial
environments. Ground fault currents greater than a presentable
threshold value will trigger an external SCR-driven circuit
breaker to interrupt the AC line and remove the fault condition.
In addition to detection of conventional hot wire to ground faults,
the neutral fault condition is also detected.
Full advantage of the U.S. UL943 timing specification is taken
to insure maximum immunity to false triggering due to line noise.
Special features include circuitry that rapidly resets the timing
capacitor in the event that noise pulses introduce unwanted
charging currents and a memory circuit that allows firing of even
a sluggish breaker on either half-cycle of the line voltage when
external full-wave rectification is used.
FEATURES
* Internal power supply shunt regulator
* Externally programmable fault current threshold
* Externally programmable fault current integration time
* Direct interface to SCR
* Operates under line reversal; both load vs line and hot
vs neutral
www.DataSheet4U.com
* Detects neutral line faults
DIP-8
SOP-8
PIN CONFIGURATION
SCR Trigger 1
INVERTING INPUT 2
NON-INVERTING INPUT 3
GND 4
8 Vcc
7 TIMING CAPACITOR
6 SENSE ITIVITY SET RESISTOR
5 SENSE AMPLIFIER OUTPUT
UTC
UNISONIC TECHNOLOGIES CO., LTD. 1
QW-R122-007,A
1 page  
UTC LM1851
LINEAR INTEGRATED CIRCUIT
APPLICATION CIRCUITS
A typical ground fault interrupter circuit is shown in Figure 2. It is designed to operate on 120 VAC line voltage with
5 mA normal fault sensitivity.
A full-wave rectifier bridge and a 15k/2W resistor are used to supply the DC power required by the IC. A 1μF
capacitor at pin 8 used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of
the SCR on either half-cycle. When a fault causes the SCR to trigger, the circuit breaker is energized and line
voltage is removed from the load. At this time no fault current flows and the IC discharge current increases from ITH
to 3ITH ( see Circuit Description and Block Diagram ). This quickly resets both the timing capacitor and the output
latch. At this time the circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault
has been removed. A 1000:1 sense transformer is used to detect the normal fault. The fault current, which is
basically the difference current between the hot and neutral lines, is stepped down by 1000 and fed into the input
pins of the operational amplifier through a 10μF capacitor. The 0.0033μF capacitor between pin 2 and pin 3 and
the 200 pF between pins 3 and 4 are added to obtain better noise immunity. The normal fault sensitivity is
determined by the timing capacitor discharging current, ITH. ITH can be calculated by:
ITH=
7V
RSET
÷2
(1)
At the decision point, the average fault current just equals the threshold current, ITH.
ITH=
If (rms)
2
× 0.91
(2)
Where If(rms) is the rms input fault current to the operational amp and the factor of 2 is due to the fact that If
charges the timing capacitor only during one half-cycle, while ITH discharges the capacitor continuously. The factor
0.91 converts the rms value to an average value. Combining equations (1) and (2) we have
RSET=
7V
If (rms) × 0.91
(3)
For example, to obtain 5mA (rms) sensitivity for the circuit in Figure 2 we have:
RSET=
7V
5mA × 0.91
=1.5MΩ
1000
(4)
The correct value for RSET can also be determined from the characteristic curve that plots equation (3). Note that
this is an approximate calculation; the exact value of RSET depends on the specific sense transformer used and UTC
LM1851 tolerances. Inasmuch as UL943 specifies a sensitivity '' window '' of 4mA ~ 6mA, provision should be made
to adjust RSET on a per-product basis.
Independent of setting sensitivity, the desired integration time can be obtained through proper selection of the
timing capacitor, Ct. Due to the large number of variables involved, proper selection of Ct is best done empirically.
The following design example, then should only be used as a guideline.
Assume the goal is to meet UL943 timing requirements. Also assume that worst-case timing occurs during GF1
Start-up (S1 closure) with both a heavy normal fault and a 2Ω grounded neutral fault present. This situation is
shown diagrammatically below.
UTC
UNISONIC TECHNOLOGIES CO., LTD. 5
QW-R122-007,A
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet LM1851.PDF ] | |
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